[AArch64][SVE] Add ABS support

For some reason we missed ABS out of the list of supported integer
operations when adding the SVE port initially.

2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs.
	(SVE_FP_UNARY): Sort.

gcc/testsuite/
	* gcc.target/aarch64/pr64946.c: Force nosve.
	* gcc.target/aarch64/ssadv16qi.c: Likewise.
	* gcc.target/aarch64/usadv16qi.c: Likewise.
	* gcc.target/aarch64/vect-abs-compile.c: Likewise.
	* gcc.target/aarch64/sve/abs_1.c: New test.

From-SVN: r267304

8 files changed, 45 insertions, 4 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d9c5c6..5fa350f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs.
+	(SVE_FP_UNARY): Sort.
+
+2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* config/aarch64/aarch64-sve.md (*cond_<optab><mode>_4): Use
 	sve_fmla_op rather than sve_fmad_op for the movprfx alternative.
 
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index ae75666..a16b74c 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1209,10 +1209,10 @@
 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
 
 ;; SVE integer unary operations.
-(define_code_iterator SVE_INT_UNARY [neg not popcount])
+(define_code_iterator SVE_INT_UNARY [abs neg not popcount])
 
 ;; SVE floating-point unary operations.
-(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
+(define_code_iterator SVE_FP_UNARY [abs neg sqrt])
 
 ;; SVE integer binary operations.
 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
@@ -1401,6 +1401,7 @@
 			      (mult "mul")
 			      (div "sdiv")
 			      (udiv "udiv")
+			      (abs "abs")
 			      (neg "neg")
 			      (smin "smin")
 			      (smax "smax")
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index da6182c..2cfdd7b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,13 @@
 2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* gcc.target/aarch64/pr64946.c: Force nosve.
+	* gcc.target/aarch64/ssadv16qi.c: Likewise.
+	* gcc.target/aarch64/usadv16qi.c: Likewise.
+	* gcc.target/aarch64/vect-abs-compile.c: Likewise.
+	* gcc.target/aarch64/sve/abs_1.c: New test.
+
+2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* gcc.target/aarch64/sve/fmla_2.c: New test.
 	* gcc.target/aarch64/sve/fmla_2_run.c: Likewise
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pr64946.c b/gcc/testsuite/gcc.target/aarch64/pr64946.c
index 736656f..ae79c0c 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr64946.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr64946.c
@@ -1,7 +1,8 @@
-
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 signed char a[100],b[100];
 void absolute_s8 (void)
 {
diff --git a/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c b/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c
index bab7599..40b2884 100644
--- a/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c
+++ b/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c
@@ -1,6 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 #define N 1024
 
 signed char pix1[N], pix2[N];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abs_1.c
new file mode 100644
index 0000000..03ebe25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abs_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <stdint.h>
+
+#define DO_OPS(TYPE)					\
+void vneg_##TYPE (TYPE *dst, TYPE *src, int count)	\
+{							\
+  for (int i = 0; i < count; ++i)			\
+    dst[i] = src[i] < 0 ? -src[i] : src[i];		\
+}
+
+DO_OPS (int8_t)
+DO_OPS (int16_t)
+DO_OPS (int32_t)
+DO_OPS (int64_t)
+
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/usadv16qi.c b/gcc/testsuite/gcc.target/aarch64/usadv16qi.c
index b7c08ee..69ceaf4 100644
--- a/gcc/testsuite/gcc.target/aarch64/usadv16qi.c
+++ b/gcc/testsuite/gcc.target/aarch64/usadv16qi.c
@@ -1,6 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 #define N 1024
 
 unsigned char pix1[N], pix2[N];
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
index 19082d7..8d4bf2a 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
@@ -1,7 +1,8 @@
-
 /* { dg-do compile } */
 /* { dg-options "-O3 -fno-vect-cost-model" } */
 
+#pragma GCC target "+nosve"
+
 #define N 16
 
 #include "vect-abs.x"