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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2016-12-16 16:26:08 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2016-12-16 16:26:08 +0000 |
| commit | 680153bd1eefcdd31809fedd9a937bff03853dcf (patch) | |
| tree | 00be7995ada4c57e55b468434321eaaa9a451aaf /gcc | |
| parent | bcb036c515a43d2c3ded6399aa486fbc3d7f8a76 (diff) | |
| download | gcc-680153bd1eefcdd31809fedd9a937bff03853dcf.zip gcc-680153bd1eefcdd31809fedd9a937bff03853dcf.tar.gz gcc-680153bd1eefcdd31809fedd9a937bff03853dcf.tar.bz2 | |
[AArch64] Split X-reg UBFIZ into W-reg LSL when possible
* config/aarch64/aarch64.md: New define_split above bswap<mode>2.
* gcc.target/aarch64/ubfiz_lsl_1.c: New test.
From-SVN: r243756
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 18 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c | 13 |
4 files changed, 39 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d7f39fc..9aecfdc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * config/aarch64/aarch64.md: New define_split above bswap<mode>2. + +2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * config/aarch64/aarch64.md: New define_split above insv<mode>. 2016-12-16 Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 078bd8e..6d89e31 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4439,6 +4439,24 @@ [(set_attr "type" "bfx")] ) +;; When the bit position and width of the equivalent extraction add up to 32 +;; we can use a W-reg LSL instruction taking advantage of the implicit +;; zero-extension of the X-reg. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand 2 "const_int_operand")) + (match_operand 3 "const_int_operand")))] + "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2]) + && (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3]))) + == GET_MODE_BITSIZE (SImode)" + [(set (match_dup 0) + (zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))] + { + operands[4] = gen_lowpart (SImode, operands[1]); + } +) + (define_insn "bswap<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fc73346..30f8931 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * gcc.target/aarch64/ubfiz_lsl_1.c: New test. + +2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * gcc.target/aarch64/ubfx_lsr_1.c: New test. 2016-12-16 Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c new file mode 100644 index 0000000..d3fd3f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL. */ + +long long +f2 (long long x) +{ + return (x << 5) & 0xffffffff; +} + +/* { dg-final { scan-assembler "lsl\tw" } } */ +/* { dg-final { scan-assembler-not "ubfiz\tx" } } */ |