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author | Vladimir Makarov <vmakarov@redhat.com> | 2018-12-07 16:08:17 +0000 |
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committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 2018-12-07 16:08:17 +0000 |
commit | 66a0970a1f728399bc81b38b845e2045605a2294 (patch) | |
tree | ae48781718d95c1ceaae788a0dfadcc323fb7828 /gcc | |
parent | 29f0d7d457668f1a6acd3bd8b9ac67d37315d999 (diff) | |
download | gcc-66a0970a1f728399bc81b38b845e2045605a2294.zip gcc-66a0970a1f728399bc81b38b845e2045605a2294.tar.gz gcc-66a0970a1f728399bc81b38b845e2045605a2294.tar.bz2 |
re PR rtl-optimization/88349 ([MIPS] Redundant store instructions generated start with r266385)
2018-12-07 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/88349
* ira-costs.c (record_operand_costs): Check bigger reg class on
NO_REGS.
2018-12-07 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/88349
* gcc.target/mips/pr88349.c: New.
From-SVN: r266894
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/ira-costs.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/mips/pr88349.c | 14 |
4 files changed, 28 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 95c1a4a..3bdbf56 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-12-07 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/88349 + * ira-costs.c (record_operand_costs): Check bigger reg class on + NO_REGS. + 2018-12-07 Richard Sandiford <richard.sandiford@arm.com> * config/aarch64/aarch64-sve.md (*mul<mode>3, *v<optab><mode>3): diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index d0f097b..14d0ff3 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1327,8 +1327,9 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref) fit the the hard reg class (e.g. DImode for AREG on i386). Check this and use a bigger class to get the right cost. */ - if (! ira_hard_reg_in_set_p (other_regno, mode, - reg_class_contents[hard_reg_class])) + if (bigger_hard_reg_class != NO_REGS + && ! ira_hard_reg_in_set_p (other_regno, mode, + reg_class_contents[hard_reg_class])) hard_reg_class = bigger_hard_reg_class; i = regno == (int) REGNO (src) ? 1 : 0; for (k = cost_classes_ptr->num - 1; k >= 0; k--) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fd940b4..8ad888d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-12-07 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/88349 + * gcc.target/mips/pr88349.c: New. + 2018-12-07 Jakub Jelinek <jakub@redhat.com> PR c++/86669 diff --git a/gcc/testsuite/gcc.target/mips/pr88349.c b/gcc/testsuite/gcc.target/mips/pr88349.c new file mode 100644 index 0000000..f070d24 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr88349.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mel -mabi=32 -march=mips64r2 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +__attribute__((mips16)) SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} + +/* { dg-final { scan-assembler-not "\tsw\t" } } */ |