Revert commit r249424 2017-06-20 Carl Love <cel@us.ibm.com>

gcc/ChangeLog:

2017-07-17  Carl Love  <cel@us.ibm.com>

	Revert commit r249424	2017-06-20  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW,
	ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries.
	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin,
	builtin_function_type): Add ALTIVEC_BUILTIN_* case statements.
	* config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW,
	VMULOSW): New enum "unspec" values.
	(vec_widen_umult_even_v4si, vec_widen_smult_even_v4si,
	vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si,
	altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw,
	altivec_vmulosw): New patterns.
	* config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW,
	VMULOSW): Add definitions.

gcc/testsuite/ChangeLog:

2017-07-17  Carl Love  <cel@us.ibm.com>

	Revert commit r249572 	2017-06-22 Carl Love  <cel@us.ibm.com>
	test case changes for commit 249424

	* gcc.target/powerpc/builtins-2.c (vmulosh, vmulouh, vmulesh,
	vmuleuh): Fix scan-assembler-times should check for word not half word
	instructions.

From-SVN: r250295

7 files changed, 38 insertions, 115 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9f49c07..80a02d1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+gcc/ChangeLog:
+
+2017-07-17  Carl Love  <cel@us.ibm.com>
+
+	Revert commit r249424	2017-06-20  Carl Love  <cel@us.ibm.com>
+
+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+	ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW,
+	ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries.
+	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin,
+	builtin_function_type): Add ALTIVEC_BUILTIN_* case statements.
+	* config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW,
+	VMULOSW): New enum "unspec" values.
+	(vec_widen_umult_even_v4si, vec_widen_smult_even_v4si,
+	vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si,
+	altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw,
+	altivec_vmulosw): New patterns.
+	* config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW,
+	VMULOSW): Add definitions.
 2017-07-17  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/alpha/alpha.c: Include predict.h.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index d5f7a8f..91c5651 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -36,14 +36,10 @@
    UNSPEC_VMULESB
    UNSPEC_VMULEUH
    UNSPEC_VMULESH
-   UNSPEC_VMULEUW
-   UNSPEC_VMULESW
    UNSPEC_VMULOUB
    UNSPEC_VMULOSB
    UNSPEC_VMULOUH
    UNSPEC_VMULOSH
-   UNSPEC_VMULOUW
-   UNSPEC_VMULOSW
    UNSPEC_VPKPX
    UNSPEC_VPACK_SIGN_SIGN_SAT
    UNSPEC_VPACK_SIGN_UNS_SAT
@@ -1418,32 +1414,6 @@
   DONE;
 })
 
-(define_expand "vec_widen_umult_even_v4si"
-  [(use (match_operand:V2DI 0 "register_operand" ""))
-   (use (match_operand:V4SI 1 "register_operand" ""))
-   (use (match_operand:V4SI 2 "register_operand" ""))]
- "TARGET_ALTIVEC"
-{
-  if (VECTOR_ELT_ORDER_BIG)
-    emit_insn (gen_altivec_vmuleuw (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_altivec_vmulouw (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "vec_widen_smult_even_v4si"
-  [(use (match_operand:V2DI 0 "register_operand" ""))
-   (use (match_operand:V4SI 1 "register_operand" ""))
-   (use (match_operand:V4SI 2 "register_operand" ""))]
-  "TARGET_ALTIVEC"
-{
-  if (VECTOR_ELT_ORDER_BIG)
-    emit_insn (gen_altivec_vmulesw (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_altivec_vmulosw (operands[0], operands[1], operands[2]));
-  DONE;
-})
-
 (define_expand "vec_widen_umult_odd_v16qi"
   [(use (match_operand:V8HI 0 "register_operand" ""))
    (use (match_operand:V16QI 1 "register_operand" ""))
@@ -1496,34 +1466,6 @@
   DONE;
 })
 
-(define_expand "vec_widen_umult_odd_v4si"
-  [(use (match_operand:V2DI 0 "register_operand" ""))
-   (use (match_operand:V4SI 1 "register_operand" ""))
-   (use (match_operand:V4SI 2 "register_operand" ""))]
-  "TARGET_ALTIVEC"
-{
-  if (VECTOR_ELT_ORDER_BIG)
-    emit_insn (gen_altivec_vmulouw (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_altivec_vmuleuw (operands[0], operands[1], operands[2]));
-  DONE;
-})
-
-(define_expand "vec_widen_smult_odd_v4si"
-  [(use (match_operand:V2DI 0 "register_operand" ""))
-   (use (match_operand:V4SI 1 "register_operand" ""))
-   (use (match_operand:V4SI 2 "register_operand" ""))]
-  "TARGET_ALTIVEC"
-{
-  if (VECTOR_ELT_ORDER_BIG)
-    emit_insn (gen_altivec_vmulosw (operands[0], operands[1],
-				    operands[2]));
-  else
-    emit_insn (gen_altivec_vmulesw (operands[0], operands[1],
-				    operands[2]));
-  DONE;
-})
-
 (define_insn "altivec_vmuleub"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
@@ -1596,41 +1538,6 @@
   "vmulosh %0,%1,%2"
   [(set_attr "type" "veccomplex")])
 
-(define_insn "altivec_vmuleuw"
-  [(set (match_operand:V2DI 0 "register_operand" "=v")
-	(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
-		      (match_operand:V4SI 2 "register_operand" "v")]
-		     UNSPEC_VMULEUW))]
-  "TARGET_ALTIVEC"
-  "vmuleuw %0,%1,%2"
-  [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulouw"
-  [(set (match_operand:V2DI 0 "register_operand" "=v")
-	(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
-		      (match_operand:V4SI 2 "register_operand" "v")]
-		     UNSPEC_VMULOUW))]
-  "TARGET_ALTIVEC"
-  "vmulouw %0,%1,%2"
-  [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulesw"
-  [(set (match_operand:V2DI 0 "register_operand" "=v")
-	(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
-		      (match_operand:V4SI 2 "register_operand" "v")]
-		     UNSPEC_VMULESW))]
-  "TARGET_ALTIVEC"
-  "vmulesw %0,%1,%2"
-  [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulosw"
-  [(set (match_operand:V2DI 0 "register_operand" "=v")
-	(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
-		      (match_operand:V4SI 2 "register_operand" "v")]
-		     UNSPEC_VMULOSW))]
-  "TARGET_ALTIVEC"
-  "vmulosw %0,%1,%2"
-  [(set_attr "type" "veccomplex")])
 
 ;; Vector pack/unpack
 (define_insn "altivec_vpkpx"
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index f2ff76b..bf2c90b 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1031,14 +1031,10 @@ BU_ALTIVEC_2 (VMULEUB,	      "vmuleub",	CONST,	vec_widen_umult_even_v16qi)
 BU_ALTIVEC_2 (VMULESB,	      "vmulesb",	CONST,	vec_widen_smult_even_v16qi)
 BU_ALTIVEC_2 (VMULEUH,	      "vmuleuh",	CONST,	vec_widen_umult_even_v8hi)
 BU_ALTIVEC_2 (VMULESH,	      "vmulesh",	CONST,	vec_widen_smult_even_v8hi)
-BU_ALTIVEC_2 (VMULEUW,	      "vmuleuw",	CONST,	vec_widen_umult_even_v4si)
-BU_ALTIVEC_2 (VMULESW,	      "vmulesw",	CONST,	vec_widen_smult_even_v4si)
 BU_ALTIVEC_2 (VMULOUB,	      "vmuloub",	CONST,	vec_widen_umult_odd_v16qi)
 BU_ALTIVEC_2 (VMULOSB,	      "vmulosb",	CONST,	vec_widen_smult_odd_v16qi)
 BU_ALTIVEC_2 (VMULOUH,	      "vmulouh",	CONST,	vec_widen_umult_odd_v8hi)
 BU_ALTIVEC_2 (VMULOSH,	      "vmulosh",	CONST,	vec_widen_smult_odd_v8hi)
-BU_ALTIVEC_2 (VMULOUW,	      "vmulouw",	CONST,	vec_widen_umult_odd_v4si)
-BU_ALTIVEC_2 (VMULOSW,	      "vmulosw",	CONST,	vec_widen_smult_odd_v4si)
 BU_ALTIVEC_2 (VNOR,	      "vnor",		CONST,	norv4si3)
 BU_ALTIVEC_2 (VOR,	      "vor",		CONST,	iorv4si3)
 BU_ALTIVEC_2 (VPKUHUM,	      "vpkuhum",	CONST,	altivec_vpkuhum)
@@ -1357,16 +1353,12 @@ BU_ALTIVEC_OVERLOAD_2 (VMRGLH,	   "vmrglh")
 BU_ALTIVEC_OVERLOAD_2 (VMRGLW,	   "vmrglw")
 BU_ALTIVEC_OVERLOAD_2 (VMULESB,	   "vmulesb")
 BU_ALTIVEC_OVERLOAD_2 (VMULESH,	   "vmulesh")
-BU_ALTIVEC_OVERLOAD_2 (VMULESW,	   "vmulesw")
 BU_ALTIVEC_OVERLOAD_2 (VMULEUB,	   "vmuleub")
 BU_ALTIVEC_OVERLOAD_2 (VMULEUH,	   "vmuleuh")
-BU_ALTIVEC_OVERLOAD_2 (VMULEUW,	   "vmuleuw")
 BU_ALTIVEC_OVERLOAD_2 (VMULOSB,	   "vmulosb")
 BU_ALTIVEC_OVERLOAD_2 (VMULOSH,	   "vmulosh")
-BU_ALTIVEC_OVERLOAD_2 (VMULOSW,	   "vmulosw")
 BU_ALTIVEC_OVERLOAD_2 (VMULOUB,	   "vmuloub")
 BU_ALTIVEC_OVERLOAD_2 (VMULOUH,	   "vmulouh")
-BU_ALTIVEC_OVERLOAD_2 (VMULOUW,	   "vmulouw")
 BU_ALTIVEC_OVERLOAD_2 (VPKSHSS,	   "vpkshss")
 BU_ALTIVEC_OVERLOAD_2 (VPKSHUS,	   "vpkshus")
 BU_ALTIVEC_OVERLOAD_2 (VPKSWSS,	   "vpkswss")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 937cda0..2a36126 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2232,9 +2232,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW,
+  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW,
+  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
@@ -2251,9 +2251,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW,
+  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW,
+  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index e49a091..988926b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16358,11 +16358,9 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
     /* Even element flavors of vec_mul (signed). */
     case ALTIVEC_BUILTIN_VMULESB:
     case ALTIVEC_BUILTIN_VMULESH:
-    case ALTIVEC_BUILTIN_VMULESW:
     /* Even element flavors of vec_mul (unsigned).  */
     case ALTIVEC_BUILTIN_VMULEUB:
     case ALTIVEC_BUILTIN_VMULEUH:
-    case ALTIVEC_BUILTIN_VMULEUW:
       {
 	arg0 = gimple_call_arg (stmt, 0);
 	arg1 = gimple_call_arg (stmt, 1);
@@ -16375,11 +16373,9 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
     /* Odd element flavors of vec_mul (signed).  */
     case ALTIVEC_BUILTIN_VMULOSB:
     case ALTIVEC_BUILTIN_VMULOSH:
-    case ALTIVEC_BUILTIN_VMULOSW:
     /* Odd element flavors of vec_mul (unsigned). */
     case ALTIVEC_BUILTIN_VMULOUB:
     case ALTIVEC_BUILTIN_VMULOUH:
-    case ALTIVEC_BUILTIN_VMULOUW:
       {
 	arg0 = gimple_call_arg (stmt, 0);
 	arg1 = gimple_call_arg (stmt, 1);
@@ -18069,10 +18065,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
       /* unsigned 2 argument functions.  */
     case ALTIVEC_BUILTIN_VMULEUB:
     case ALTIVEC_BUILTIN_VMULEUH:
-    case ALTIVEC_BUILTIN_VMULEUW:
     case ALTIVEC_BUILTIN_VMULOUB:
     case ALTIVEC_BUILTIN_VMULOUH:
-    case ALTIVEC_BUILTIN_VMULOUW:
     case CRYPTO_BUILTIN_VCIPHER:
     case CRYPTO_BUILTIN_VCIPHERLAST:
     case CRYPTO_BUILTIN_VNCIPHER:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 156e78e..4bbc174 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+gcc/testsuite/ChangeLog:
+
+2017-07-17  Carl Love  <cel@us.ibm.com>
+
+	Revert commit r249572 	2017-06-22 Carl Love  <cel@us.ibm.com>
+	test case changes for commit 249424
+
+	* gcc.target/powerpc/builtins-2.c (vmulosh, vmulouh, vmulesh,
+	vmuleuh): Fix scan-assembler-times should check for word not half word
+	instructions.
+
 2017-07-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
 	PR tree-optimization/81162
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index 00fa6ec..e0e3714 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -236,8 +236,8 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
 /* { dg-final { scan-assembler-times "xvnegsp"  1 } } */
 /* { dg-final { scan-assembler-times "xvnegdp"  1 } } */
 /* { dg-final { scan-assembler-times "vslo"     4 } } */
-/* { dg-final { scan-assembler-times "vmulosw"  1 } } */
-/* { dg-final { scan-assembler-times "vmulouw"  1 } } */
-/* { dg-final { scan-assembler-times "vmulesw"  1 } } */
-/* { dg-final { scan-assembler-times "vmuleuw"  1 } } */
+/* { dang-remove { scan-assembler-times "vmulosw"  1 } } */
+/* { dang-remove  { scan-assembler-times "vmulouw"  1 } } */
+/* { dang-remove  { scan-assembler-times "vmulesw"  1 } } */
+/* { dang-remove  { scan-assembler-times "vmuleuw"  1 } } */
 /* { dg-final { scan-assembler-times "xxsldwi"  8 } } */