diff options
| author | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2016-02-19 10:37:19 +0000 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2016-02-19 10:37:19 +0000 |
| commit | 6448f0645b918b340f8b01c60b10af8409c51b56 (patch) | |
| tree | 2d37927338dd278f44747b6341b38d70a4dbce4a /gcc | |
| parent | ece33b1b76e5de7fd5c305bf602702f42f1e8bb7 (diff) | |
| download | gcc-6448f0645b918b340f8b01c60b10af8409c51b56.zip gcc-6448f0645b918b340f8b01c60b10af8409c51b56.tar.gz gcc-6448f0645b918b340f8b01c60b10af8409c51b56.tar.bz2 | |
S/390: z13 Change predicates of 128 bit add sub.
So far usage of 128 bit add/sub instruction was rejected if the second
operand was a constant because the predicate rejected this.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/int128-1.c: New test.
gcc/ChangeLog:
* config/s390/vector.md ("<ti*>add<mode>3", "<ti*>sub<mode>3"):
Change the predicate of op2 from nonimmediate to general and let
reload fix it if necessary.
From-SVN: r233554
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/s390/vector.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/s390/vector/int128-1.c | 47 |
4 files changed, 59 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06fedf0..471a01b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2016-02-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * config/s390/vector.md ("<ti*>add<mode>3", "<ti*>sub<mode>3"): + Change the predicate of op2 from nonimmediate to general and let + reload fix it if necessary. + +2016-02-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * config/s390/vecintrin.h (vec_sub_u128): Define missing macro. 2016-02-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 2302a8f..cdb9ba6 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -454,7 +454,7 @@ (define_insn "<ti*>add<mode>3" [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") - (match_operand:VIT 2 "nonimmediate_operand" "v")))] + (match_operand:VIT 2 "general_operand" "v")))] "TARGET_VX" "va<bhfgq>\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) @@ -463,7 +463,7 @@ (define_insn "<ti*>sub<mode>3" [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") (minus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") - (match_operand:VIT 2 "nonimmediate_operand" "v")))] + (match_operand:VIT 2 "general_operand" "v")))] "TARGET_VX" "vs<bhfgq>\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index abb2ed6..4a0dbab 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2016-02-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * gcc.target/s390/vector/int128-1.c: New test. + +2016-02-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * gcc.target/s390/vector/vec-vcond-1.c: New test. 2016-02-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> diff --git a/gcc/testsuite/gcc.target/s390/vector/int128-1.c b/gcc/testsuite/gcc.target/s390/vector/int128-1.c new file mode 100644 index 0000000..b4a16b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/int128-1.c @@ -0,0 +1,47 @@ +/* Check that vaq/vsq are used for int128 operations. */ + +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O3 -mzarch -march=z13" } */ + + +const __int128 c = (__int128)0x0123456789abcd55 + ((__int128)7 << 64); + + +__int128 +addreg(__int128 a, __int128 b) +{ + return a + b; +} + +__int128 +addconst(__int128 a) +{ + return a + c; +} + +__int128 +addmem(__int128 *a, __int128_t *b) +{ + return *a + *b; +} + +__int128 +subreg(__int128 a, __int128 b) +{ + return a - b; +} + +__int128 +subconst(__int128 a) +{ + return a - c; /* This becomes vaq as well. */ +} + +__int128 +submem(__int128 *a, __int128_t *b) +{ + return *a - *b; +} + +/* { dg-final { scan-assembler-times "vaq" 4 } } */ +/* { dg-final { scan-assembler-times "vsq" 2 } } */ |