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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-09-21 05:33:46 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-11-02 13:38:34 -0800 |
| commit | 6058b874ef98af1104a5cb4618e1f3bfa7e3761c (patch) | |
| tree | 1ad3bad4e081c4151b397d6cb43f17471ef5fbf0 /gcc | |
| parent | 88ce3d5fbb948cc600800b15f4ca774a0ce8e7a7 (diff) | |
| download | gcc-6058b874ef98af1104a5cb4618e1f3bfa7e3761c.zip gcc-6058b874ef98af1104a5cb4618e1f3bfa7e3761c.tar.gz gcc-6058b874ef98af1104a5cb4618e1f3bfa7e3761c.tar.bz2 | |
x86: Also require MMX for __builtin_ia32_maskmovq
MMX emulation with SEE is implemented at MMX intrinsic level, not at MMX
instruction level. _mm_maskmove_si64 intrinsic for "MASKMOVQ mm1, mm2"
is emulated with __builtin_ia32_maskmovdqu. Since SSE "MASKMOVQ mm1, mm2"
builtin function, __builtin_ia32_maskmovq, can't be emulated with XMM
registers, make __builtin_ia32_maskmovq also require MMX instead of SSE
only.
gcc/
PR target/97140
* config/i386/i386-expand.c (ix86_expand_builtin): Require MMX
for __builtin_ia32_maskmovq.
gcc/testsuite/
PR target/97140
* gcc.target/i386/pr97140.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386-expand.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr97140.c | 10 |
2 files changed, 17 insertions, 1 deletions
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 9d2eb7f..f479466 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -11074,11 +11074,17 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); - if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE) + + if ((bisa & OPTION_MASK_ISA_MMX) + && !TARGET_MMX + && TARGET_MMX_WITH_SSE + /* NB: __builtin_ia32_maskmovq also requires MMX. */ + && fcode != IX86_BUILTIN_MASKMOVQ) { bisa &= ~OPTION_MASK_ISA_MMX; bisa |= OPTION_MASK_ISA_SSE2; } + if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2) { bool add_abi_p = bisa & OPTION_MASK_ISA_64BIT; diff --git a/gcc/testsuite/gcc.target/i386/pr97140.c b/gcc/testsuite/gcc.target/i386/pr97140.c new file mode 100644 index 0000000..edb39d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr97140.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mno-mmx -Wno-psabi" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef char __v8qi __attribute__ ((__vector_size__ (8))); +void +_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P) +{ + __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); /* { dg-error "needs isa option -msse -m3dnowa -mmmx" } */ +} |