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| author | Jim Wilson <wilson@gcc.gnu.org> | 1993-07-28 11:01:25 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1993-07-28 11:01:25 -0700 |
| commit | 5fd7eed02db18b5acb5563857bc025a58b736f4b (patch) | |
| tree | 945350097588db6224ae1bd3baed6ad956fe99f1 /gcc | |
| parent | 42d93ca6b2075b50914ac89960d0af0c2db81387 (diff) | |
| download | gcc-5fd7eed02db18b5acb5563857bc025a58b736f4b.zip gcc-5fd7eed02db18b5acb5563857bc025a58b736f4b.tar.gz gcc-5fd7eed02db18b5acb5563857bc025a58b736f4b.tar.bz2 | |
(shift_operand): New function.
From-SVN: r5027
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sparc/sparc.c | 13 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 6 |
2 files changed, 16 insertions, 3 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 46946dd..ae0c45e 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -432,6 +432,19 @@ arith_double_operand (op, mode) && (unsigned) (INTVAL (op) + 0x1000) < 0x2000)); } +/* Return true if OP is a register, or is a CONST_INT that can fit in a 5 + bit unsigned immediate field. This is an acceptable SImode operand for + the count field of shift instructions. */ + +int +shift_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) + || (GET_CODE (op) == CONST_INT && (unsigned) (INTVAL (op)) < 32)); +} + /* Return truth value of whether OP is a integer which fits the range constraining immediate operands in most three-address insns, which have a 13 bit immediate field. */ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index f4e5f81..65357a9 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2538,21 +2538,21 @@ (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI")))] + (match_operand:SI 2 "shift_operand" "rI")))] "" "sll %1,%2,%0") (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI")))] + (match_operand:SI 2 "shift_operand" "rI")))] "" "sra %1,%2,%0") (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI")))] + (match_operand:SI 2 "shift_operand" "rI")))] "" "srl %1,%2,%0") |