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| author | Richard Sandiford <rsandifo@redhat.com> | 2004-05-07 15:06:16 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2004-05-07 15:06:16 +0000 |
| commit | 5c8a81d5a8a462b4648491110c0bee8ae2c89d0a (patch) | |
| tree | 7f21edb4fe5a018666bec243c12a721b9c75254f /gcc | |
| parent | 9045f39a0e63c1c253e09e02fe718450226facd6 (diff) | |
| download | gcc-5c8a81d5a8a462b4648491110c0bee8ae2c89d0a.zip gcc-5c8a81d5a8a462b4648491110c0bee8ae2c89d0a.tar.gz gcc-5c8a81d5a8a462b4648491110c0bee8ae2c89d0a.tar.bz2 | |
mips.h (ISA_HAS_BRANCHLIKELY): Remove TARGET_MIPS5500.
* config/mips/mips.h (ISA_HAS_BRANCHLIKELY): Remove TARGET_MIPS5500.
* config/mips/mips.c (override_options): Disable branch likely
instructions if TUNE_MIPS5500.
From-SVN: r81624
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 2 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 3 |
3 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 586c463..6c3ba6d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2004-05-07 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.h (ISA_HAS_BRANCHLIKELY): Remove TARGET_MIPS5500. + * config/mips/mips.c (override_options): Disable branch likely + instructions if TUNE_MIPS5500. + +2004-05-07 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.c (override_options): Allow the hi and lo registers to store any integral mode, not just MODE_INTs. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index beb7250..09d826a 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -4744,7 +4744,7 @@ override_options (void) -mbranch-likely. */ if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64) - && !(TUNE_SB1)) + && !(TUNE_MIPS5500 || TUNE_SB1)) target_flags |= MASK_BRANCHLIKELY; else target_flags &= ~MASK_BRANCHLIKELY; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e23abf1..cdde774 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -858,8 +858,7 @@ extern const struct mips_cpu_info *mips_tune_info; /* ISA has branch likely instructions (eg. mips2). */ /* Disable branchlikely for tx39 until compare rewrite. They haven't been generated up to this point. */ -#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \ - && !TARGET_MIPS5500) +#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) /* ISA has the conditional move instructions introduced in mips4. */ #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ |