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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-05 02:23:19 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-05 02:23:19 +0000 |
| commit | 5c36be57336c5d4c3b989e9be5bbe060a0deba12 (patch) | |
| tree | 2c8e17774394482c120371556d5e99af1a4f42b7 /gcc | |
| parent | 77827557f67584ca88ba16a93b224447ea234965 (diff) | |
| download | gcc-5c36be57336c5d4c3b989e9be5bbe060a0deba12.zip gcc-5c36be57336c5d4c3b989e9be5bbe060a0deba12.tar.gz gcc-5c36be57336c5d4c3b989e9be5bbe060a0deba12.tar.bz2 | |
[NDS32] The add and sub pattens should only accept si mode.
gcc/
* config/nds32/nds32.md (add<mode>3, sub<mode>3): Rename to ...
(addsi3, subsi3): ... this.
From-SVN: r259116
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.md | 16 |
2 files changed, 13 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fe76138..da7eed2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32.md (add<mode>3, sub<mode>3): Rename to ... + (addsi3, subsi3): ... this. + +2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32.md (*sub_srli, *and_slli): Fine-tune predicator. 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 0189bdf..95345ff 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -320,10 +320,10 @@ ;; Arithmetic instructions. -(define_insn "add<mode>3" - [(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") - (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") - (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))] +(define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") + (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") + (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,IU06, Is15, r")))] "" { switch (which_alternative) @@ -363,10 +363,10 @@ (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4") (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")]) -(define_insn "sub<mode>3" - [(set (match_operand:QIHISI 0 "register_operand" "=d, l, r, r") - (minus:QIHISI (match_operand:QIHISI 1 "nds32_rimm15s_operand" " 0, l, Is15, r") - (match_operand:QIHISI 2 "register_operand" " r, l, r, r")))] +(define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=d, l, r, r") + (minus:SI (match_operand:SI 1 "nds32_rimm15s_operand" " 0, l, Is15, r") + (match_operand:SI 2 "register_operand" " r, l, r, r")))] "" "@ sub45\t%0, %2 |