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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2015-01-16 04:56:27 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2015-01-16 04:56:27 +0000 |
| commit | 5a4ba50ef78f21a2439719d9cd5dfcb121f97ce8 (patch) | |
| tree | 63f807d18444c24989f9b4677486cc4e20d40fc5 /gcc | |
| parent | 679337288c80140fefbe682cb85cbff7bc271bc0 (diff) | |
| download | gcc-5a4ba50ef78f21a2439719d9cd5dfcb121f97ce8.zip gcc-5a4ba50ef78f21a2439719d9cd5dfcb121f97ce8.tar.gz gcc-5a4ba50ef78f21a2439719d9cd5dfcb121f97ce8.tar.bz2 | |
[NDS32][DOC] Describe -mcmodel= option instead of -mgp-direct in the documentation.
gcc/
* doc/invoke.texi (NDS32 Options): Add -mcmodel= option and
remove -mgp-direct option.
From-SVN: r219706
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 25 |
2 files changed, 21 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e105c44..5334bdf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-01-16 Chung-Ju Wu <jasonwucj@gmail.com> + + * doc/invoke.texi (NDS32 Options): Add -mcmodel= option and + remove -mgp-direct option. + 2015-01-15 Jan Hubicka <hubicka@ucw.cz> * doc/invoke.texi (--param early-inlining-insns): Update default value. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 12368e8e..5eee2a3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -861,10 +861,10 @@ Objective-C and Objective-C++ Dialects}. -mperf-ext -mno-perf-ext @gol -mv3push -mno-v3push @gol -m16bit -mno-16bit @gol --mgp-direct -mno-gp-direct @gol -misr-vector-size=@var{num} @gol -mcache-block-size=@var{num} @gol -march=@var{arch} @gol +-mcmodel=@var{code-model} @gol -mforce-fp-as-gp -mforbid-fp-as-gp @gol -mex9 -mctor-dtor -mrelax} @@ -19153,14 +19153,6 @@ Generate 16-bit instructions. @opindex mno-16-bit Do not generate 16-bit instructions. -@item -mgp-direct -@opindex mgp-direct -Generate GP base instructions directly. - -@item -mno-gp-direct -@opindex mno-gp-direct -Do no generate GP base instructions directly. - @item -misr-vector-size=@var{num} @opindex misr-vector-size Specify the size of each interrupt vector, which must be 4 or 16. @@ -19174,6 +19166,21 @@ which must be a power of 2 between 4 and 512. @opindex march Specify the name of the target architecture. +@item -mcmodel=@var{code-model} +@opindex mcmodel +Set the code model to one of +@table @asis +@item @samp{small} +All the data and read-only data segments must be within 512KB addressing space. +The text segment must be within 16MB addressing space. +@item @samp{medium} +The data segment must be within 512KB while the read-only data segment can be +within 4GB addressing space. The text segment should be still within 16MB +addressing space. +@item @samp{large} +All the text and data segments can be within 4GB addressing space. +@end table + @item -mforce-fp-as-gp @opindex mforce-fp-as-gp Prevent $fp being allocated during register allocation so that compiler |