arm.md (type): Add "simple_alu_shift" to attribute "type".

gcc/

2012-12-17  Greta Yorsh  <Greta.Yorsh@arm.com>

        * config/arm/arm.md (type): Add "simple_alu_shift" to attribute "type".
        (core_cycles): Update for simple_alu_shift.
        (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Use simple_alu_shift
        instead of a CPU-speicific condition for "type" attribute.
        (thumb1_zero_extendqisi2_v6,arm_zero_extendqisi2_v6): Likewise.
        (thumb1_extendhisi2,arm_extendhisi2_v6,arm_extendqisi_v6): Likewise.
        (thumb1_extendqisi2): Likewise.
        * config/arm/thumb2.md (thumb2_extendqisi_v6): Likewise.
        (thumb2_zero_extendhisi2_v6,thumb2_zero_extendqisi2_v6) Likewise.
        * config/arm/arm1020e.md (alu_shift_op): Use simple_alu_shift.
        * config/arm/arm1026ejs.md (alu_shift_op): Likewise.
        * config/arm/arm1136jfs.md (11_alu_shift_op): Likewise.
        * config/arm/arm926ejs.md (9_alu_op): Likewise.
        * config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise.
        * config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise.
        * config/arm/cortex-a8.md (cortex_a8_alu_shift,cortex_a8_mov): Likewise.
        * config/arm/cortex-a9.md (cortex_a9_dp,cortex_a9_dp_shift): Likewise.
        * config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
        * config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise.
        * config/arm/fa526.md (526_alu_shift_op): Likewise.
        * config/arm/fa606te.md (fa606te_core): Likewise.
        * config/arm/fa626te.md (626te_alu_shift_op): Likewise.
        * config/arm/fa726te.md (726te_alu_shift_op): Likewise.
        * config/arm/fmp626.md (mp626_alu_shift_op): Likewise.

From-SVN: r194557

18 files changed, 60 insertions, 74 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 47f5a01..3c0f6c4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,30 @@
+2012-12-17  Greta Yorsh  <Greta.Yorsh@arm.com>
+
+        * config/arm/arm.md (type): Add "simple_alu_shift" to attribute "type".
+        (core_cycles): Update for simple_alu_shift.
+        (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Use simple_alu_shift
+        instead of a CPU-speicific condition for "type" attribute.
+        (thumb1_zero_extendqisi2_v6,arm_zero_extendqisi2_v6): Likewise.
+        (thumb1_extendhisi2,arm_extendhisi2_v6,arm_extendqisi_v6): Likewise.
+        (thumb1_extendqisi2): Likewise.
+        * config/arm/thumb2.md (thumb2_extendqisi_v6): Likewise.
+        (thumb2_zero_extendhisi2_v6,thumb2_zero_extendqisi2_v6) Likewise.
+        * config/arm/arm1020e.md (alu_shift_op): Use simple_alu_shift.
+        * config/arm/arm1026ejs.md (alu_shift_op): Likewise.
+        * config/arm/arm1136jfs.md (11_alu_shift_op): Likewise.
+        * config/arm/arm926ejs.md (9_alu_op): Likewise.
+        * config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise.
+        * config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise.
+        * config/arm/cortex-a8.md (cortex_a8_alu_shift,cortex_a8_mov): Likewise.
+        * config/arm/cortex-a9.md (cortex_a9_dp,cortex_a9_dp_shift): Likewise.
+        * config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
+        * config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise.
+        * config/arm/fa526.md (526_alu_shift_op): Likewise.
+        * config/arm/fa606te.md (fa606te_core): Likewise.
+        * config/arm/fa626te.md (626te_alu_shift_op): Likewise.
+        * config/arm/fa726te.md (726te_alu_shift_op): Likewise.
+        * config/arm/fmp626.md (mp626_alu_shift_op): Likewise.
+
 2012-12-17  Richard Biener  <rguenther@suse.de>
 
 	PR middle-end/54781
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 7f38816..649e901 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -240,6 +240,7 @@
 ;               regs or have a shifted source operand
 ;               and does not have an immediate operand. This is
 ;               also the default
+; simple_alu_shift covers UXTH, UXTB, SXTH, SXTB
 ; alu_shift	any data instruction that doesn't hit memory or fp
 ;		regs, but has a source operand shifted by a constant
 ; alu_shift_reg	any data instruction that doesn't hit memory or fp
@@ -271,6 +272,7 @@
 (define_attr "type"
  "simple_alu_imm,\
   alu_reg,\
+  simple_alu_shift,\
   alu_shift,\
   alu_shift_reg,\
   mult,\
@@ -454,7 +456,9 @@
 ; than one on the main cpu execution unit.
 (define_attr "core_cycles" "single,multi"
   (if_then_else (eq_attr "type"
-		 "simple_alu_imm,alu_reg,alu_shift,float,fdivd,fdivs")
+		 "simple_alu_imm,alu_reg,\
+                  simple_alu_shift,alu_shift,\
+                  float,fdivd,fdivs")
 		(const_string "single")
 	        (const_string "multi")))
 
@@ -4629,11 +4633,7 @@
 			 [(if_then_else (eq_attr "is_arch6" "yes")
 				       (const_int 2) (const_int 4))
 			 (const_int 4)])
-   (set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])]
+   (set_attr "type" "simple_alu_shift, load_byte")]
 )
 
 (define_insn "*arm_zero_extendhisi2"
@@ -4655,11 +4655,7 @@
    uxth%?\\t%0, %1
    ldr%(h%)\\t%0, %1"
   [(set_attr "predicable" "yes")
-   (set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])]
+   (set_attr "type" "simple_alu_shift,load_byte")]
 )
 
 (define_insn "*arm_zero_extendhisi2addsi"
@@ -4729,11 +4725,7 @@
    uxtb\\t%0, %1
    ldrb\\t%0, %1"
   [(set_attr "length" "2")
-   (set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])]
+   (set_attr "type" "simple_alu_shift,load_byte")]
 )
 
 (define_insn "*arm_zero_extendqisi2"
@@ -4755,11 +4747,7 @@
   "@
    uxtb%(%)\\t%0, %1
    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
-  [(set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+  [(set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "predicable" "yes")]
 )
 
@@ -4933,11 +4921,7 @@
 			 [(if_then_else (eq_attr "is_arch6" "yes")
 					(const_int 2) (const_int 4))
 			  (const_int 4)])
-   (set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+   (set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "pool_range" "*,1018")]
 )
 
@@ -5010,11 +4994,7 @@
   "@
    sxth%?\\t%0, %1
    ldr%(sh%)\\t%0, %1"
-  [(set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+  [(set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,256")
    (set_attr "neg_pool_range" "*,244")]
@@ -5114,11 +5094,7 @@
   "@
    sxtb%?\\t%0, %1
    ldr%(sb%)\\t%0, %1"
-  [(set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+  [(set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,256")
    (set_attr "neg_pool_range" "*,244")]
@@ -5231,12 +5207,7 @@
 			  (const_int 2)
 			  (if_then_else (eq_attr "is_arch6" "yes")
 					(const_int 4) (const_int 6))])
-   (set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")
-                          (const_string "load_byte")])]
+   (set_attr "type" "simple_alu_shift,load_byte,load_byte")]
 )
 
 (define_expand "extendsfdf2"
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 3d3ff23..9a41d30 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -72,7 +72,7 @@
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "1020alu_shift_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu_shift"))
+      (eq_attr "type" "simple_alu_shift,alu_shift"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-register operand
diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md
index d9ed858..52f6241 100644
--- a/gcc/config/arm/arm1026ejs.md
+++ b/gcc/config/arm/arm1026ejs.md
@@ -72,7 +72,7 @@
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "alu_shift_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "alu_shift"))
+      (eq_attr "type" "simple_alu_shift,alu_shift"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-register operand
diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md
index ff5e614..9e88558 100644
--- a/gcc/config/arm/arm1136jfs.md
+++ b/gcc/config/arm/arm1136jfs.md
@@ -81,7 +81,7 @@
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "11_alu_shift_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "alu_shift"))
+      (eq_attr "type" "simple_alu_shift,alu_shift"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-register operand
diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md
index 656a90e..4c94e33 100644
--- a/gcc/config/arm/arm926ejs.md
+++ b/gcc/config/arm/arm926ejs.md
@@ -58,7 +58,7 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "9_alu_op" 1 
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift"))
+      (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift"))
  "e,m,w")
 
 ;; ALU operations with a shift-by-register operand
diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md
index f25fcee..33e53df 100644
--- a/gcc/config/arm/cortex-a15.md
+++ b/gcc/config/arm/cortex-a15.md
@@ -68,7 +68,7 @@
 ;; ALU ops with immediate shift
 (define_insn_reservation "cortex_a15_alu_shift" 3
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "alu_shift")
+       (and (eq_attr "type" "simple_alu_shift,alu_shift")
             (eq_attr "neon_type" "none")))
   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
 	       |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 1121c7e..2b5abe5 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -63,7 +63,7 @@
 
 (define_insn_reservation "cortex_a5_alu_shift" 2
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
   "cortex_a5_ex1")
 
 ;; Forwarding path for unshifted operands.
diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index 7c266d3..73c61b1 100644
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -93,7 +93,7 @@
 
 (define_insn_reservation "cortex_a8_alu_shift" 2
   (and (eq_attr "tune" "cortexa8")
-       (and (eq_attr "type" "alu_shift")
+       (and (eq_attr "type" "simple_alu_shift,alu_shift")
             (not (eq_attr "insn" "mov,mvn"))))
   "cortex_a8_default")
 
@@ -107,7 +107,7 @@
 
 (define_insn_reservation "cortex_a8_mov" 1
   (and (eq_attr "tune" "cortexa8")
-       (and (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg")
+       (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")
             (eq_attr "insn" "mov,mvn")))
   "cortex_a8_default")
 
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 336c4fc..f1bd7cf 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -82,7 +82,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
   (and (eq_attr "tune" "cortexa9")
          (ior (and (eq_attr "type" "alu_reg,simple_alu_imm")
                         (eq_attr "neon_type" "none"))
-	      (and (and (eq_attr "type" "alu_shift_reg, alu_shift")
+	      (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
 			(eq_attr "insn" "mov"))
                  (eq_attr "neon_type" "none"))))
   "cortex_a9_p0_default|cortex_a9_p1_default")
@@ -90,7 +90,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
 ;; An instruction using the shifter will go down E1.
 (define_insn_reservation "cortex_a9_dp_shift" 3
    (and (eq_attr "tune" "cortexa9")
-	(and (eq_attr "type" "alu_shift_reg, alu_shift")
+	(and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
 	     (not (eq_attr "insn" "mov"))))
    "cortex_a9_p0_shift | cortex_a9_p1_shift")
 
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index bff17dd..063fe5f 100644
--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -31,7 +31,7 @@
 ;; ALU and multiply is one cycle.
 (define_insn_reservation "cortex_m4_alu" 1
   (and (eq_attr "tune" "cortexm4")
-       (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg,mult"))
+       (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg,mult"))
   "cortex_m4_ex")
 
 ;; Byte, half-word and word load is two cycles.
diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md
index 26de65a..a870dc0 100644
--- a/gcc/config/arm/cortex-r4.md
+++ b/gcc/config/arm/cortex-r4.md
@@ -90,7 +90,7 @@
 
 (define_insn_reservation "cortex_r4_alu_shift" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (eq_attr "type" "alu_shift"))
+       (eq_attr "type" "simple_alu_shift,alu_shift"))
   "cortex_r4_alu")
 
 (define_insn_reservation "cortex_r4_alu_shift_reg" 2
diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md
index 2b89bb5..8108522 100644
--- a/gcc/config/arm/fa526.md
+++ b/gcc/config/arm/fa526.md
@@ -67,7 +67,7 @@
 
 (define_insn_reservation "526_alu_shift_op" 2
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "alu_shift,alu_shift_reg"))
+      (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
  "fa526_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md
index 4725b93..d995b1d 100644
--- a/gcc/config/arm/fa606te.md
+++ b/gcc/config/arm/fa606te.md
@@ -62,7 +62,7 @@
 ;; ALU operations
 (define_insn_reservation "606te_alu_op" 1
  (and (eq_attr "tune" "fa606te")
-      (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg"))
+      (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg"))
  "fa606te_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md
index bed3995..6b01b06 100644
--- a/gcc/config/arm/fa626te.md
+++ b/gcc/config/arm/fa626te.md
@@ -73,7 +73,7 @@
 
 (define_insn_reservation "626te_alu_shift_op" 2
  (and (eq_attr "tune" "fa626,fa626te")
-      (eq_attr "type" "alu_shift,alu_shift_reg"))
+      (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
  "fa626te_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md
index a4c256c..7c898ab 100644
--- a/gcc/config/arm/fa726te.md
+++ b/gcc/config/arm/fa726te.md
@@ -95,7 +95,7 @@
 ;; it takes 3 cycles.
 (define_insn_reservation "726te_alu_shift_op" 3
  (and (eq_attr "tune" "fa726te")
-      (and (eq_attr "type" "alu_shift")
+      (and (eq_attr "type" "simple_alu_shift,alu_shift")
            (not (eq_attr "insn" "mov,mvn"))))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 
diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md
index 228817c..f63b6bf 100644
--- a/gcc/config/arm/fmp626.md
+++ b/gcc/config/arm/fmp626.md
@@ -68,7 +68,7 @@
 
 (define_insn_reservation "mp626_alu_shift_op" 2
  (and (eq_attr "tune" "fmp626")
-      (eq_attr "type" "alu_shift,alu_shift_reg"))
+      (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
  "fmp626_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index f22666c..d4dd1b9 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -570,11 +570,7 @@
   "@
    sxtb%?\\t%0, %1
    ldr%(sb%)\\t%0, %1"
-  [(set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+  [(set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -587,11 +583,7 @@
   "@
    uxth%?\\t%0, %1
    ldr%(h%)\\t%0, %1"
-  [(set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+  [(set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -604,11 +596,7 @@
   "@
    uxtb%(%)\\t%0, %1
    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
-  [(set_attr_alternative "type"
-                         [(if_then_else (eq_attr "tune" "cortexa7")
-                                        (const_string "simple_alu_imm")
-                                        (const_string "alu_shift"))
-                          (const_string "load_byte")])
+  [(set_attr "type" "simple_alu_shift,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]