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| author | Andrey Belevantsev <abel@ispras.ru> | 2012-11-09 16:28:21 +0400 |
|---|---|---|
| committer | Andrey Belevantsev <abel@gcc.gnu.org> | 2012-11-09 16:28:21 +0400 |
| commit | 50919d13a394428f3c1394863c5e13e23e3a6fb0 (patch) | |
| tree | ad89d2d191dbe38d1655bcc74af37b05a1d19c16 /gcc | |
| parent | 4e568a151c146de62c58f35cd4620145600e4bf2 (diff) | |
| download | gcc-50919d13a394428f3c1394863c5e13e23e3a6fb0.zip gcc-50919d13a394428f3c1394863c5e13e23e3a6fb0.tar.gz gcc-50919d13a394428f3c1394863c5e13e23e3a6fb0.tar.bz2 | |
re PR rtl-optimization/54472 (ICE (spill_failure): unable to find a register to spill in class 'AREG' with -O -fschedule-insns -fselective-scheduling)
PR rtl-optimization/54472
* sel-sched-ir.c (has_dependence_note_reg_set): Handle implicit sets.
(has_dependence_note_reg_clobber,
has_dependence_note_reg_use): Likewise.
* gcc.dg/pr54472.c: New test.
From-SVN: r193358
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/sel-sched-ir.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr54472.c | 9 |
4 files changed, 26 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f8f19ba..37566fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2012-11-09 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/54472 + + * sel-sched-ir.c (has_dependence_note_reg_set): Handle implicit sets. + (has_dependence_note_reg_clobber, + has_dependence_note_reg_use): Likewise. + 2012-11-09 Eric Botcazou <ebotcazou@adacore.com> * config/i386/i386.c (release_scratch_register_on_entry): Also adjust diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 7b0f512..e0239dc 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -3185,7 +3185,7 @@ has_dependence_note_reg_set (int regno) || reg_last->clobbers != NULL) *dsp = (*dsp & ~SPECULATIVE) | DEP_OUTPUT; - if (reg_last->uses) + if (reg_last->uses || reg_last->implicit_sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; } } @@ -3205,7 +3205,7 @@ has_dependence_note_reg_clobber (int regno) if (reg_last->sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_OUTPUT; - if (reg_last->uses) + if (reg_last->uses || reg_last->implicit_sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; } } @@ -3225,7 +3225,7 @@ has_dependence_note_reg_use (int regno) if (reg_last->sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_TRUE; - if (reg_last->clobbers) + if (reg_last->clobbers || reg_last->implicit_sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; /* Merge BE_IN_SPEC bits into *DSP when the dependency producer diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 226c5f8..cdf47a9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2012-11-09 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/54472 + + * gcc.dg/pr54472.c: New test. + 2012-11-09 Eric Botcazou <ebotcazou@adacore.com> * gnat.dg/stack_check3.ad[sb]: New test. diff --git a/gcc/testsuite/gcc.dg/pr54472.c b/gcc/testsuite/gcc.dg/pr54472.c new file mode 100644 index 0000000..9395203 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr54472.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns -fselective-scheduling" } */ + +int main () +{ + int a[3][3][3]; + __builtin_memset (a, 0, sizeof a); + return 0; +} |