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| author | Richard Henderson <rth@redhat.com> | 2005-08-11 09:56:32 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2005-08-11 09:56:32 -0700 |
| commit | 4ead2a39a3dcee6901040ada8a8832963490138d (patch) | |
| tree | be2f651ce696cc5b1fe0aa1136a6d348a5ac8e06 /gcc | |
| parent | da8ce8be372a2ca4220120b81fe6a1d79a54ea75 (diff) | |
| download | gcc-4ead2a39a3dcee6901040ada8a8832963490138d.zip gcc-4ead2a39a3dcee6901040ada8a8832963490138d.tar.gz gcc-4ead2a39a3dcee6901040ada8a8832963490138d.tar.bz2 | |
re PR target/22225 (Tru64 UNIX testsuite failure: gcc.dg/vect/pr18536.c: ICE in in alphaev4_insn_pipe)
PR target/22225
* config/alpha/alpha.c (alphaev4_insn_pipe): Add take pipes for
insn types not present on ev4.
(alphaev5_insn_pipe): Similarly.
From-SVN: r102996
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.c | 12 |
2 files changed, 19 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f2f72f5..753f3ce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2005-08-11 Richard Henderson <rth@redhat.com> + + PR target/22225 + * config/alpha/alpha.c (alphaev4_insn_pipe): Add take pipes for + insn types not present on ev4. + (alphaev5_insn_pipe): Similarly. + 2005-08-11 Richard Earnshaw <richard.earnshaw@arm.com> PR target/23250 diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 7d8faa5..f15964f 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -8731,6 +8731,11 @@ alpha_handle_trap_shadows (void) /* Alpha can only issue instruction groups simultaneously if they are suitably aligned. This is very processor-specific. */ +/* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe + that are marked "fake". These instructions do not exist on that target, + but it is possible to see these insns with deranged combinations of + command-line options, such as "-mtune=ev4 -mmax". Instead of aborting, + choose a result at random. */ enum alphaev4_pipe { EV4_STOP = 0, @@ -8774,6 +8779,7 @@ alphaev4_insn_pipe (rtx insn) case TYPE_SHIFT: case TYPE_IMUL: case TYPE_FBR: + case TYPE_MVI: /* fake */ return EV4_IB0; case TYPE_IST: @@ -8788,6 +8794,9 @@ alphaev4_insn_pipe (rtx insn) case TYPE_FMUL: case TYPE_ST_C: case TYPE_MB: + case TYPE_FSQRT: /* fake */ + case TYPE_FTOI: /* fake */ + case TYPE_ITOF: /* fake */ return EV4_IB1; default: @@ -8823,6 +8832,8 @@ alphaev5_insn_pipe (rtx insn) case TYPE_LD_L: case TYPE_ST_C: case TYPE_MB: + case TYPE_FTOI: /* fake */ + case TYPE_ITOF: /* fake */ return EV5_E0; case TYPE_IBR: @@ -8837,6 +8848,7 @@ alphaev5_insn_pipe (rtx insn) case TYPE_FCMOV: case TYPE_FADD: case TYPE_FDIV: + case TYPE_FSQRT: /* fake */ return EV5_FA; case TYPE_FMUL: |