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| author | Michael Eager <eager@eagercon.com> | 2017-03-09 18:09:39 +0000 |
|---|---|---|
| committer | Michael Eager <eager@gcc.gnu.org> | 2017-03-09 18:09:39 +0000 |
| commit | 4e0c6654ef99fe34a012dbb9507db33f51e8fde8 (patch) | |
| tree | a6749334366eb089afef19124ffda15fce9e4e0a /gcc | |
| parent | c9819d22705d43ced3c05763172812061cdddce9 (diff) | |
| download | gcc-4e0c6654ef99fe34a012dbb9507db33f51e8fde8.zip gcc-4e0c6654ef99fe34a012dbb9507db33f51e8fde8.tar.gz gcc-4e0c6654ef99fe34a012dbb9507db33f51e8fde8.tar.bz2 | |
Correct failures with --enable-checking=yes,rtl.
* config/microblaze/microblaze.c (microblaze_expand_shift):
Replace GET_CODE test with CONST_INT_P and INTVAL test with
test for const0_rtx.
* config/microblaze/microblaze.md (ashlsi3_byone, ashrsi3_byone,
lshrsi3_byone): Replace INTVAL with test for const1_rtx.
From-SVN: r246012
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/microblaze/microblaze.c | 6 | ||||
| -rw-r--r-- | gcc/config/microblaze/microblaze.md | 6 |
3 files changed, 16 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2c1b515..96fb28b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-03-09 Michael Eager <eager@eagercon.com> + + Correct failures with --enable-checking=yes,rtl. + + * config/microblaze/microblaze.c (microblaze_expand_shift): + Replace GET_CODE test with CONST_INT_P and INTVAL test with + test for const0_rtx. + * config/microblaze/microblaze.md (ashlsi3_byone, ashrsi3_byone, + lshrsi3_byone): Replace INTVAL with test for const1_rtx. + 2017-03-09 Richard Biener <rguenther@suse.de> PR tree-optimization/79977 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index 746bef1..fb115e6 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -3323,10 +3323,10 @@ microblaze_expand_shift (rtx operands[]) || (GET_CODE (operands[1]) == SUBREG)); /* Shift by zero -- copy regs if necessary. */ - if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 0)) + if (CONST_INT_P (operands[2]) && (operands[2] == const0_rtx) + && !rtx_equal_p (operands[0], operands[1])) { - if (REGNO (operands[0]) != REGNO (operands[1])) - emit_insn (gen_movsi (operands[0], operands[1])); + emit_insn (gen_movsi (operands[0], operands[1])); return 1; } diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 66ebc1e..b3a0011 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1321,7 +1321,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "arith_operand" "I")))] - "(INTVAL (operands[2]) == 1)" + "(operands[2] == const1_rtx)" "addk\t%0,%1,%1" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -1482,7 +1482,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "arith_operand" "I")))] - "(INTVAL (operands[2]) == 1)" + "(operands[2] == const1_rtx)" "sra\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -1571,7 +1571,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "arith_operand" "I")))] - "(INTVAL (operands[2]) == 1)" + "(operands[2] == const1_rtx)" "srl\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI") |