i386.md (*bt<mode>): Macroize insn from *btsi and *btdi_rex64 using SWI48 mode iterator.

	* config/i386/i386.md (*bt<mode>): Macroize insn from *btsi and
	*btdi_rex64 using SWI48 mode iterator.
	(*jcc_bt<mode>): Ditto from *jcc_btsi and *jcc_btdi_rex64.
	(*jcc_bt<mode>_mask): Ditto from *jcc_btsi_mask and
	*jcc_btdi_mask_rex64.

From-SVN: r158438

2 files changed, 34 insertions, 100 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bbce851..cbf1340 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2010-04-16  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*bt<mode>): Macroize insn from *btsi and
+	*btdi_rex64 using SWI48 mode iterator.
+	(*jcc_bt<mode>): Ditto from *jcc_btsi and *jcc_btdi_rex64.
+	(*jcc_bt<mode>_mask): Ditto from *jcc_btsi_mask and
+	*jcc_btdi_mask_rex64.
+
 2010-04-16  Anatoly Sokolov  <aesok@post.ru>
 
 	* double-int.h (tree_to_double_int): Convert to macro.
@@ -303,7 +311,7 @@
 	(logic): Ditto from logicprefix.
 	(absneg_mnemonic): Ditto from absnegprefix.
 	* config/i386/mmx.md: Update all users of maxminiprefix,
-	maxminfprefix and loficprefix for rename.
+	maxminfprefix and logicprefix for rename.
 	* config/i386/sse.md: Ditto.
 	* config/i386/sync.md (sync_<code><mode>): Update for
 	logicprefix rename.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3f29325..d142c7f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10965,33 +10965,19 @@
   DONE;
 })
 
-(define_insn "*btdi_rex64"
+(define_insn "*bt<mode>"
   [(set (reg:CCC FLAGS_REG)
 	(compare:CCC
-	  (zero_extract:DI
-	    (match_operand:DI 0 "register_operand" "r")
+	  (zero_extract:SWI48
+	    (match_operand:SWI48 0 "register_operand" "r")
 	    (const_int 1)
-	    (match_operand:DI 1 "nonmemory_operand" "rN"))
-	  (const_int 0)))]
-  "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
-  "bt{q}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")
-   (set_attr "mode" "DI")])
-
-(define_insn "*btsi"
-  [(set (reg:CCC FLAGS_REG)
-	(compare:CCC
-	  (zero_extract:SI
-	    (match_operand:SI 0 "register_operand" "r")
-	    (const_int 1)
-	    (match_operand:SI 1 "nonmemory_operand" "rN"))
+	    (match_operand:SWI48 1 "nonmemory_operand" "rN"))
 	  (const_int 0)))]
   "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
-  "bt{l}\t{%1, %0|%0, %1}"
+  "bt{<imodesuffix>}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "<MODE>")])
 
 ;; Store-flag instructions.
 
@@ -11248,16 +11234,16 @@
     FAIL;
 })
 
-;; zero_extend in SImode is correct, since this is what combine pass
-;; generates from shift insn with QImode operand.  Actually, the mode of
-;; operand 2 (bit offset operand) doesn't matter since bt insn takes
+;; zero_extend in SImode is correct also for DImode, since this is what combine
+;; pass generates from shift insn with QImode operand.  Actually, the mode
+;; of operand 2 (bit offset operand) doesn't matter since bt insn takes
 ;; appropriate modulo of the bit offset value.
 
-(define_insn_and_split "*jcc_btdi_rex64"
+(define_insn_and_split "*jcc_bt<mode>"
   [(set (pc)
   	(if_then_else (match_operator 0 "bt_comparison_operator"
-			[(zero_extract:DI
-			   (match_operand:DI 1 "register_operand" "r")
+			[(zero_extract:SWI48
+			   (match_operand:SWI48 1 "register_operand" "r")
 			   (const_int 1)
 			   (zero_extend:SI
 			     (match_operand:QI 2 "register_operand" "r")))
@@ -11265,12 +11251,12 @@
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
+  "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
   "#"
   "&& 1"
   [(set (reg:CCC FLAGS_REG)
 	(compare:CCC
-	  (zero_extract:DI
+	  (zero_extract:SWI48
 	    (match_dup 1)
 	    (const_int 1)
 	    (match_dup 2))
@@ -11280,17 +11266,18 @@
 		      (label_ref (match_dup 3))
 		      (pc)))]
 {
-  operands[2] = simplify_gen_subreg (DImode, operands[2], QImode, 0);
+  operands[2] = simplify_gen_subreg (<MODE>mode, operands[2], QImode, 0);
 
   PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
 })
 
-;; avoid useless masking of bit offset operand
-(define_insn_and_split "*jcc_btdi_mask_rex64"
+;; Avoid useless masking of bit offset operand.  "and" in SImode is correct
+;; also for DImode, this is what combine produces.
+define_insn_and_split "*jcc_bt<mode>_mask"
   [(set (pc)
   	(if_then_else (match_operator 0 "bt_comparison_operator"
-			[(zero_extract:DI
-			   (match_operand:DI 1 "register_operand" "r")
+			[(zero_extract:SWI48
+			   (match_operand:SWI48 1 "register_operand" "r")
 			   (const_int 1)
 			   (and:SI
 			     (match_operand:SI 2 "register_operand" "r")
@@ -11298,13 +11285,14 @@
 		      (label_ref (match_operand 4 "" ""))
 		      (pc)))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))
-   && (INTVAL (operands[3]) & 0x3f) == 0x3f"
+  "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
+   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
+      == GET_MODE_BITSIZE (<MODE>mode)-1"
   "#"
   "&& 1"
   [(set (reg:CCC FLAGS_REG)
 	(compare:CCC
-	  (zero_extract:DI
+	  (zero_extract:SWI48
 	    (match_dup 1)
 	    (const_int 1)
 	    (match_dup 2))
@@ -11314,73 +11302,11 @@
 		      (label_ref (match_dup 4))
 		      (pc)))]
 {
-  operands[2] = simplify_gen_subreg (DImode, operands[2], SImode, 0);
-
-  PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
-})
-
-(define_insn_and_split "*jcc_btsi"
-  [(set (pc)
-  	(if_then_else (match_operator 0 "bt_comparison_operator"
-			[(zero_extract:SI
-			   (match_operand:SI 1 "register_operand" "r")
-			   (const_int 1)
-			   (zero_extend:SI
-			     (match_operand:QI 2 "register_operand" "r")))
-			 (const_int 0)])
-		      (label_ref (match_operand 3 "" ""))
-		      (pc)))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
-  "#"
-  "&& 1"
-  [(set (reg:CCC FLAGS_REG)
-	(compare:CCC
-	  (zero_extract:SI
-	    (match_dup 1)
-	    (const_int 1)
-	    (match_dup 2))
-	  (const_int 0)))
-   (set (pc)
-	(if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
-		      (label_ref (match_dup 3))
-		      (pc)))]
-{
-  operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
+  operands[2] = simplify_gen_subreg (<MODE>mode, operands[2], SImode, 0);
 
   PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
 })
 
-;; avoid useless masking of bit offset operand
-(define_insn_and_split "*jcc_btsi_mask"
-  [(set (pc)
-  	(if_then_else (match_operator 0 "bt_comparison_operator"
-			[(zero_extract:SI
-			   (match_operand:SI 1 "register_operand" "r")
-			   (const_int 1)
-			   (and:SI
-			     (match_operand:SI 2 "register_operand" "r")
-			     (match_operand:SI 3 "const_int_operand" "n")))])
-		      (label_ref (match_operand 4 "" ""))
-		      (pc)))
-   (clobber (reg:CC FLAGS_REG))]
-  "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
-   && (INTVAL (operands[3]) & 0x1f) == 0x1f"
-  "#"
-  "&& 1"
-  [(set (reg:CCC FLAGS_REG)
-	(compare:CCC
-	  (zero_extract:SI
-	    (match_dup 1)
-	    (const_int 1)
-	    (match_dup 2))
-	  (const_int 0)))
-   (set (pc)
-	(if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
-		      (label_ref (match_dup 4))
-		      (pc)))]
-  "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
-
 (define_insn_and_split "*jcc_btsi_1"
   [(set (pc)
   	(if_then_else (match_operator 0 "bt_comparison_operator"