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authorH.J. Lu <hongjiu.lu@intel.com>2019-02-16 20:29:24 +0000
committerH.J. Lu <hjl@gcc.gnu.org>2019-02-16 12:29:24 -0800
commit49be11f5c9376c0b3ee0b4f8a1cc19ca797e9f45 (patch)
tree1946270e460d26ec172c43cf94f602018051f240 /gcc
parent843192c0ebde5cc6e4f1abeb02e3ac05b02d984a (diff)
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i386: Correct *vec_extractv2si_zext_mem
The second and third alternatives in *vec_extractv2si_zext_mem don't require MMX. But the second one requires SSE2. * config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require MMX. Add isa attribute. From-SVN: r268963
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/i386/mmx.md5
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index addbd39..58e991d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require
+ MMX. Add isa attribute.
+
2019-02-16 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/66152
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index c1e0f2c..b566cc8 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1354,13 +1354,14 @@
(vec_select:SI
(match_operand:V2SI 1 "memory_operand" "o,o,o")
(parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
- "TARGET_64BIT && TARGET_MMX"
+ "TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
{
operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
-})
+}
+ [(set_attr "isa" "*,sse2,*")])
(define_expand "vec_extractv2sisi"
[(match_operand:SI 0 "register_operand")