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| author | Ilya Enkovich <enkovich.gnu@gmail.com> | 2016-01-18 10:35:56 +0000 |
|---|---|---|
| committer | Ilya Enkovich <ienkovich@gcc.gnu.org> | 2016-01-18 10:35:56 +0000 |
| commit | 3dd5f42e90fa6e296d233b0f05c3a760a45d1313 (patch) | |
| tree | cc8cc97b2e96f6eb8cdb733c094748674ddca8c2 /gcc | |
| parent | ae5a77fa960564c8a5b2a00c22b38d954aecddb8 (diff) | |
| download | gcc-3dd5f42e90fa6e296d233b0f05c3a760a45d1313.zip gcc-3dd5f42e90fa6e296d233b0f05c3a760a45d1313.tar.gz gcc-3dd5f42e90fa6e296d233b0f05c3a760a45d1313.tar.bz2 | |
i386.c (scalar_to_vector_candidate_p): Support andnot instruction.
gcc/
* config/i386/i386.c (scalar_to_vector_candidate_p): Support
andnot instruction.
(scalar_chain::convert_op): Likewise.
* config/i386/i386.md (*andndi3_doubleword): New.
gcc/testsuite/
* gcc.target/i386/pr65105-5.c: Adjust to andn generation.
From-SVN: r232500
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 13 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 17 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr65105-5.c | 2 |
5 files changed, 40 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1cc9288..b2522c1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-01-18 Ilya Enkovich <enkovich.gnu@gmail.com> + + * config/i386/i386.c (scalar_to_vector_candidate_p): Support + andnot instruction. + (scalar_chain::convert_op): Likewise. + * config/i386/i386.md (*andndi3_doubleword): New. + 2016-01-18 Richard Biener <rguenther@suse.de> PR tree-optimization/69170 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index ff976dd..92d8ee1 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2815,7 +2815,11 @@ scalar_to_vector_candidate_p (rtx_insn *insn) return false; } - if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0))) + if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0)) + /* Check for andnot case. */ + && (GET_CODE (src) != AND + || GET_CODE (XEXP (src, 0)) != NOT + || !REG_P (XEXP (XEXP (src, 0), 0)))) return false; if (!REG_P (XEXP (src, 1)) && !MEM_P (XEXP (src, 1))) @@ -3383,7 +3387,12 @@ scalar_chain::convert_op (rtx *op, rtx_insn *insn) { *op = copy_rtx_if_shared (*op); - if (MEM_P (*op)) + if (GET_CODE (*op) == NOT) + { + convert_op (&XEXP (*op, 0), insn); + PUT_MODE (*op, V2DImode); + } + else if (MEM_P (*op)) { rtx tmp = gen_reg_rtx (DImode); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 71941d0..f16b42a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -8645,6 +8645,23 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") +(define_insn_and_split "*andndi3_doubleword" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (and:DI + (not:DI (match_operand:DI 1 "register_operand" "r,r")) + (match_operand:DI 2 "nonimmediate_operand" "r,m"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 3) + (and:SI (not:SI (match_dup 4)) (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + (define_insn "*<code>hi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k") (any_or:HI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7d93a493..498632d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2016-01-18 Ilya Enkovich <enkovich.gnu@gmail.com> + + * gcc.target/i386/pr65105-5.c: Adjust to andn generation. + 2016-01-18 Eric Botcazou <ebotcazou@adacore.com> * gnat.dg/inline12.adb: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr65105-5.c b/gcc/testsuite/gcc.target/i386/pr65105-5.c index 5818c1c..639bbe1 100644 --- a/gcc/testsuite/gcc.target/i386/pr65105-5.c +++ b/gcc/testsuite/gcc.target/i386/pr65105-5.c @@ -1,7 +1,7 @@ /* PR target/pr65105 */ /* { dg-do compile { target { ia32 } } } */ /* { dg-options "-O2 -march=core-avx2" } */ -/* { dg-final { scan-assembler "pand" } } */ +/* { dg-final { scan-assembler "pandn" } } */ /* { dg-final { scan-assembler "pxor" } } */ /* { dg-final { scan-assembler "ptest" } } */ |