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| author | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2014-08-27 11:14:16 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2014-08-27 11:14:16 +0000 |
| commit | 38f4b55004b0e6c7ffc5a8138db457ce5df12ff1 (patch) | |
| tree | da504fa051abea76ccc31686d3541044c4a83d37 /gcc | |
| parent | 07f1cf564b3b64096998da79ea1963e100688a0e (diff) | |
| download | gcc-38f4b55004b0e6c7ffc5a8138db457ce5df12ff1.zip gcc-38f4b55004b0e6c7ffc5a8138db457ce5df12ff1.tar.gz gcc-38f4b55004b0e6c7ffc5a8138db457ce5df12ff1.tar.bz2 | |
sse.md (define_mode_iterator VI48_AVX2_48_AVX512F): Delete.
gcc/
* config/i386/sse.md
(define_mode_iterator VI48_AVX2_48_AVX512F): Delete.
(define_mode_iterator VI48_AVX512BW): New.
(define_insn "<avx2_avx512f>_<shift_insn>v<mode><mask_name>"): Delete.
(define_insn "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>"
with VI48_AVX2_48_AVX512F): New.
(define_insn "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>"
with VI2_AVX512VL): Ditto.
Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r214569
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 18 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 27 |
2 files changed, 37 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3156965..ded0288 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2014-08-27 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + + * config/i386/sse.md + (define_mode_iterator VI48_AVX2_48_AVX512F): Delete. + (define_mode_iterator VI48_AVX512BW): New. + (define_insn "<avx2_avx512f>_<shift_insn>v<mode><mask_name>"): Delete. + (define_insn "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>" + with VI48_AVX2_48_AVX512F): New. + (define_insn "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>" + with VI2_AVX512VL): Ditto. + 2014-08-27 Richard Biener <rguenther@suse.de> PR middle-end/62239 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5084892..cd0c08e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -359,9 +359,9 @@ (V8SI "TARGET_AVX2") V4SI (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) -(define_mode_iterator VI48_AVX2_48_AVX512F - [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI - (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) +(define_mode_iterator VI48_AVX512F + [(V16SI "TARGET_AVX512F") V8SI V4SI + (V8DI "TARGET_AVX512F") V4DI V2DI]) (define_mode_iterator V48_AVX2 [V4SF V2DF @@ -15320,17 +15320,28 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<avx2_avx512f>_<shift_insn>v<mode><mask_name>" - [(set (match_operand:VI48_AVX2_48_AVX512F 0 "register_operand" "=v") - (any_lshift:VI48_AVX2_48_AVX512F - (match_operand:VI48_AVX2_48_AVX512F 1 "register_operand" "v") - (match_operand:VI48_AVX2_48_AVX512F 2 "nonimmediate_operand" "vm")))] +(define_insn "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>" + [(set (match_operand:VI48_AVX512F 0 "register_operand" "=v") + (any_lshift:VI48_AVX512F + (match_operand:VI48_AVX512F 1 "register_operand" "v") + (match_operand:VI48_AVX512F 2 "nonimmediate_operand" "vm")))] "TARGET_AVX2 && <mask_mode512bit_condition>" "vp<vshift>v<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseishft") (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>" + [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") + (any_lshift:VI2_AVX512VL + (match_operand:VI2_AVX512VL 1 "register_operand" "v") + (match_operand:VI2_AVX512VL 2 "nonimmediate_operand" "vm")))] + "TARGET_AVX512BW" + "vp<vshift>v<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sseishft") + (set_attr "prefix" "maybe_evex") + (set_attr "mode" "<sseinsnmode>")]) + ;; For avx_vec_concat<mode> insn pattern (define_mode_attr concat_tg_mode [(V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t") |