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| author | Jakub Jelinek <jakub@redhat.com> | 2021-02-05 10:39:03 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2021-02-05 10:39:03 +0100 |
| commit | 37876976b0511ec96741f638f160874f2added0e (patch) | |
| tree | 75a96acb28e6ccb10feb80d1e0875725efc5c927 /gcc | |
| parent | b229baa75ce4627d1bd38f2d3dcd91af1a7071db (diff) | |
| download | gcc-37876976b0511ec96741f638f160874f2added0e.zip gcc-37876976b0511ec96741f638f160874f2added0e.tar.gz gcc-37876976b0511ec96741f638f160874f2added0e.tar.bz2 | |
i386: Fix up TARGET_QIMODE_MATH for many AMD CPU tunings [PR98957]
As written in the PR, TARGET_QIMODE_MATH was meant to be set for all
tunings and it was the case for GCC <= 7, but as the number of
PROCESSOR_* enumerators grew, some AMD tunings (which are at the end
of the list) over time got enumerators with values >= 32 and
TARGET_QIMODE_MATH became disabled for them, in GCC 8 for 2
tunings, in GCC 9 for 7 tunings, in GCC 10 for 8 tunings, and
on the trunk for 11 tunings.
The following patch fixes it by using uhwis rather than uints
and gives them also symbolic names.
2021-02-05 Jakub Jelinek <jakub@redhat.com>
PR target/98957
* config/i386/i386-options.c (m_NONE, m_ALL): Define.
* config/i386/x86-tune.def (X86_TUNE_BRANCH_PREDICTION_HINTS,
X86_TUNE_PROMOTE_QI_REGS): Use m_NONE instead of 0U.
(X86_TUNE_QIMODE_MATH): Use m_ALL instead of ~0U.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386-options.c | 2 | ||||
| -rw-r--r-- | gcc/config/i386/x86-tune.def | 6 |
2 files changed, 5 insertions, 3 deletions
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index a70f6ed..cdeabbf 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -98,6 +98,8 @@ along with GCC; see the file COPYING3. If not see #endif /* Processor feature/optimization bitmasks. */ +#define m_NONE HOST_WIDE_INT_0U +#define m_ALL (~HOST_WIDE_INT_0U) #define m_386 (HOST_WIDE_INT_1U<<PROCESSOR_I386) #define m_486 (HOST_WIDE_INT_1U<<PROCESSOR_I486) #define m_PENT (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM) diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index f0e07c0..140ccb3 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -580,15 +580,15 @@ DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode", on simulation result. But after P4 was made, no performance benefit was observed with branch hints. It also increases the code size. As a result, icc never generates branch hints. */ -DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0U) +DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", m_NONE) /* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */ -DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0U) +DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", m_ALL) /* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme is usually used for RISC targets. */ -DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0U) +DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", m_NONE) /* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion before a transfer of control flow out of the function. */ |