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| author | Jiawei <jiawei@iscas.ac.cn> | 2022-09-08 09:50:49 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-30 23:09:16 +0800 |
| commit | 32f86f2b54dc97cb6a40edef421b6a30c3bd1c04 (patch) | |
| tree | 1500e2972004b198efe625515ea966a34c3a355b /gcc | |
| parent | 1e2c124d71ac051373a30495793883c45bcc5415 (diff) | |
| download | gcc-32f86f2b54dc97cb6a40edef421b6a30c3bd1c04.zip gcc-32f86f2b54dc97cb6a40edef421b6a30c3bd1c04.tar.gz gcc-32f86f2b54dc97cb6a40edef421b6a30c3bd1c04.tar.bz2 | |
RISC-V: Add '-m[no]-csr-check' option in gcc.
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options.
* doc/invoke.texi: New definations.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 6 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 6 |
3 files changed, 17 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0d61831..200ad60 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5440,6 +5440,11 @@ riscv_file_start (void) if (! riscv_mrelax) fprintf (asm_out_file, "\t.option norelax\n"); + /* If the user specifies "-mcsr-check" on the command line then enable csr + check in the assembler. */ + if (riscv_mcsr_check) + fprintf (asm_out_file, "\t.option csr-check\n"); + if (riscv_emit_attribute_p) riscv_emit_attribute (); } diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index e3af561..8923a11 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. +mcsr-check +Target Bool Var(riscv_mcsr_check) Init(0) +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. +The ISA-dependent CSR are only valid when the specific ISA is set. The +read-only CSR can not be written by the CSR instructions. + Mask(64BIT) Mask(MUL) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 518bfdf..a5dc637 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1226,6 +1226,7 @@ See RS/6000 and PowerPC Options. -mbig-endian -mlittle-endian @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol -mstack-protector-guard-offset=@var{offset}} +-mcsr-check -mno-csr-check @gol @emph{RL78 Options} @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol @@ -28605,6 +28606,11 @@ linker relaxations. Emit (do not emit) RISC-V attribute to record extra information into ELF objects. This feature requires at least binutils 2.32. +@item -mcsr-check +@itemx -mno-csr-check +@opindex mcsr-check +Enables or disables the CSR checking. + @item -malign-data=@var{type} @opindex malign-data Control how GCC aligns variables and constants of array, structure, or union |