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| author | Richard Earnshaw <rearnsha@arm.com> | 2004-05-14 21:45:59 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2004-05-14 21:45:59 +0000 |
| commit | 3053b100f99e18e0254c8ad2642bca539b9a2cd7 (patch) | |
| tree | 37ae522d8ccd42905cf4d85c160502c9ac5d51e8 /gcc | |
| parent | 1cd29ad23586b888af0c47d11c33b6f6b50481c6 (diff) | |
| download | gcc-3053b100f99e18e0254c8ad2642bca539b9a2cd7.zip gcc-3053b100f99e18e0254c8ad2642bca539b9a2cd7.tar.gz gcc-3053b100f99e18e0254c8ad2642bca539b9a2cd7.tar.bz2 | |
arm.md (all peephole2 patterns): Use predicates that validate register classes as appropriate.
* arm.md (all peephole2 patterns): Use predicates that validate
register classes as appropriate.
From-SVN: r81860
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 33 |
2 files changed, 19 insertions, 19 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f327a76..01e0c66 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-05-14 Richard Earnshaw <rearnsha@arm.com> + + * arm.md (all peephole2 patterns): Use predicates that validate + register classes as appropriate. + 2004-05-14 Steven Bosscher <stevenb@suse.de> PR opt/14472 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 554b332..dadc228 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -466,8 +466,8 @@ ; addition. (define_peephole2 [(match_scratch:SI 3 "r") - (set (match_operand:SI 0 "s_register_operand" "") - (plus:SI (match_operand:SI 1 "s_register_operand" "") + (set (match_operand:SI 0 "arm_general_register_operand" "") + (plus:SI (match_operand:SI 1 "arm_general_register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] "TARGET_ARM && !(const_ok_for_arm (INTVAL (operands[2])) @@ -534,15 +534,14 @@ ;; Reloading and elimination of the frame pointer can ;; sometimes cause this optimization to be missed. (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "arm_general_register_operand" "") (match_operand:SI 1 "const_int_operand" "")) (set (match_dup 0) - (plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "")))] + (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))] "TARGET_THUMB - && REGNO (operands[2]) == STACK_POINTER_REGNUM && (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024 && (INTVAL (operands[1]) & 3) == 0" - [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))] + [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))] "" ) @@ -630,8 +629,8 @@ ;; similarly for the beq variant using bcc. ;; This is a common looping idiom (while (n--)) (define_peephole2 - [(set (match_operand:SI 0 "s_register_operand" "") - (plus:SI (match_operand:SI 1 "s_register_operand" "") + [(set (match_operand:SI 0 "arm_general_register_operand" "") + (plus:SI (match_operand:SI 1 "arm_general_register_operand" "") (const_int -1))) (set (match_operand 2 "cc_register" "") (compare (match_dup 0) (const_int -1))) @@ -986,9 +985,9 @@ (define_peephole2 [(match_scratch:SI 3 "r") - (set (match_operand:SI 0 "s_register_operand" "") + (set (match_operand:SI 0 "arm_general_register_operand" "") (minus:SI (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "s_register_operand" "")))] + (match_operand:SI 2 "arm_general_register_operand" "")))] "TARGET_ARM && !const_ok_for_arm (INTVAL (operands[1])) && const_ok_for_arm (~INTVAL (operands[1]))" @@ -2116,8 +2115,8 @@ (define_peephole2 [(match_scratch:SI 3 "r") - (set (match_operand:SI 0 "s_register_operand" "") - (ior:SI (match_operand:SI 1 "s_register_operand" "") + (set (match_operand:SI 0 "arm_general_register_operand" "") + (ior:SI (match_operand:SI 1 "arm_general_register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] "TARGET_ARM && !const_ok_for_arm (INTVAL (operands[2])) @@ -9651,15 +9650,11 @@ ; This pattern is never tried by combine, so do it as a peephole (define_peephole2 - [(set (match_operand:SI 0 "s_register_operand" "") - (match_operand:SI 1 "s_register_operand" "")) + [(set (match_operand:SI 0 "arm_general_register_operand" "") + (match_operand:SI 1 "arm_general_register_operand" "")) (set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))] - "TARGET_ARM - && (!(TARGET_HARD_FLOAT && TARGET_MAVERICK) - || (!cirrus_fp_register (operands[0], SImode) - && !cirrus_fp_register (operands[1], SImode))) - " + "TARGET_ARM" [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0))) (set (match_dup 0) (match_dup 1))])] "" |