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authorUros Bizjak <uros@gcc.gnu.org>2017-07-25 16:48:55 +0200
committerUros Bizjak <uros@gcc.gnu.org>2017-07-25 16:48:55 +0200
commit2efb42140524778738f6591330f7a6d6ecfa6287 (patch)
tree8f176d1c227b7486704dbdb63bd8587c7595f8be /gcc
parenta8697b270e4cf3a34dbf23c16952b070b7d73c09 (diff)
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i386.c (ix86_decompose_address): Do not check for register RTX when looking at index_reg or base_reg.
* config/i386/i386.c (ix86_decompose_address): Do not check for register RTX when looking at index_reg or base_reg. * config/i386/i386.h (INCOMING_RETURN_ADDR_RTX): Use stack_pointer_rtx. From-SVN: r250526
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog11
-rw-r--r--gcc/config/i386/i386.c24
-rw-r--r--gcc/config/i386/i386.h2
3 files changed, 20 insertions, 17 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb7b47d..aa3cb92 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-07-25 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (ix86_decompose_address): Do not check for
+ register RTX when looking at index_reg or base_reg.
+ * config/i386/i386.h (INCOMING_RETURN_ADDR_RTX): Use stack_pointer_rtx.
+
2017-07-25 Eric Botcazou <ebotcazou@adacore.com>
* gimple.c (gimple_assign_set_rhs_with_ops): Do not ask gsi_replace
@@ -96,8 +102,9 @@
2017-07-25 Martin Liska <mliska@suse.cz>
PR ipa/81520
- * ipa-visibility.c (function_and_variable_visibility): Make the redirection
- just on target that do supporting aliasing. Fix GNU coding style.
+ * ipa-visibility.c (function_and_variable_visibility): Make the
+ redirection just on target that supports aliasing.
+ Fix GNU coding style.
2017-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index b7ef554..084b4a6 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -13594,8 +13594,7 @@ ix86_minimum_incoming_stack_boundary (bool sibcall)
{
unsigned int incoming_stack_boundary;
- /* Stack of interrupt handler is aligned to 128 bits in 64bit
- mode. */
+ /* Stack of interrupt handler is aligned to 128 bits in 64bit mode. */
if (cfun->machine->func_type != TYPE_NORMAL)
incoming_stack_boundary = TARGET_64BIT ? 128 : MIN_STACK_BOUNDARY;
/* Prefer the one specified at command line. */
@@ -16187,9 +16186,9 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
/* Allow arg pointer and stack pointer as index if there is not scaling. */
if (base_reg && index_reg && scale == 1
- && (index_reg == arg_pointer_rtx
- || index_reg == frame_pointer_rtx
- || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
+ && (REGNO (index_reg) == ARG_POINTER_REGNUM
+ || REGNO (index_reg) == FRAME_POINTER_REGNUM
+ || REGNO (index_reg) == SP_REG))
{
std::swap (base, index);
std::swap (base_reg, index_reg);
@@ -16197,14 +16196,11 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
/* Special case: %ebp cannot be encoded as a base without a displacement.
Similarly %r13. */
- if (!disp
- && base_reg
- && (base_reg == hard_frame_pointer_rtx
- || base_reg == frame_pointer_rtx
- || base_reg == arg_pointer_rtx
- || (REG_P (base_reg)
- && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
- || REGNO (base_reg) == R13_REG))))
+ if (!disp && base_reg
+ && (REGNO (base_reg) == ARG_POINTER_REGNUM
+ || REGNO (base_reg) == FRAME_POINTER_REGNUM
+ || REGNO (base_reg) == BP_REG
+ || REGNO (base_reg) == R13_REG))
disp = const0_rtx;
/* Special case: on K6, [%esi] makes the instruction vector decoded.
@@ -16213,7 +16209,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
to test cfun for being non-NULL. */
if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
&& base_reg && !index_reg && !disp
- && REG_P (base_reg) && REGNO (base_reg) == SI_REG)
+ && REGNO (base_reg) == SI_REG)
disp = const0_rtx;
/* Special case: encode reg+reg instead of reg*2. */
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index a2ae9b4..682745a 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2165,7 +2165,7 @@ extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
/* Before the prologue, RA is at 0(%esp). */
#define INCOMING_RETURN_ADDR_RTX \
- gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM))
+ gen_rtx_MEM (Pmode, stack_pointer_rtx)
/* After the prologue, RA is at -4(AP) in the current frame. */
#define RETURN_ADDR_RTX(COUNT, FRAME) \