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| author | Kito Cheng <kito.cheng@sifive.com> | 2021-10-28 00:27:39 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-10-28 14:53:50 +0800 |
| commit | 2dc835cd0b5183a0e30b2b052362ad05f5c082b0 (patch) | |
| tree | b125c734f4184eb1c1f69dee86a4c9a0ddd320f0 /gcc | |
| parent | e399cde6f9c89cafbbf6c3274c0af3c369d4f872 (diff) | |
| download | gcc-2dc835cd0b5183a0e30b2b052362ad05f5c082b0.zip gcc-2dc835cd0b5183a0e30b2b052362ad05f5c082b0.tar.gz gcc-2dc835cd0b5183a0e30b2b052362ad05f5c082b0.tar.bz2 | |
RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern
We're wrongly guard zero_extendsidi2_internal pattern both ZBA and ZBB,
only ZBA provide zero_extendsidi2 instruction.
gcc/ChangeLog
* config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
use this pattern.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index dd4c242..225e5b2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1311,7 +1311,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)" + "TARGET_64BIT && !TARGET_ZBA" "@ # lwu\t%0,%1" |