AVX-512. 52.1/n. Add vec2mask and mask2vec insn.

gcc/
	* config/i386/predicates.md (define_predicate "constm1_operand"): New.
	* config/i386/sse.md
	(define_c_enum "unspec"): Add UNSPEC_CVTINT2MASK.
	(define_insn "<avx512>_cvt<ssemodesuffix>2mask<VI12_AVX512VL:mode>"): New.
	(define_insn "<avx512>_cvt<ssemodesuffix>2mask<VI48_AVX512VL:mode>"): Ditto.
	(define_expand "<avx512>_cvtmask2<ssemodesuffix><VI12_AVX512VL:mode>"): Ditto.
	(define_insn "*<avx512>_cvtmask2<ssemodesuffix><VI12_AVX512VL:mode>"): Ditto.
	(define_expand "<avx512>_cvtmask2<ssemodesuffix><VI48_AVX512VL:mode>"): Ditto.
	(define_insn "*<avx512>_cvtmask2<ssemodesuffix><VI48_AVX512VL:mode>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216254

3 files changed, 95 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 96b1e96..283c0d3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2014-10-15  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* config/i386/predicates.md (define_predicate "constm1_operand"): New.
+	* config/i386/sse.md
+	(define_c_enum "unspec"): Add UNSPEC_CVTINT2MASK.
+	(define_insn "<avx512>_cvt<ssemodesuffix>2mask<VI12_AVX512VL:mode>"): New.
+	(define_insn "<avx512>_cvt<ssemodesuffix>2mask<VI48_AVX512VL:mode>"): Ditto.
+	(define_expand "<avx512>_cvtmask2<ssemodesuffix><VI12_AVX512VL:mode>"): Ditto.
+	(define_insn "*<avx512>_cvtmask2<ssemodesuffix><VI12_AVX512VL:mode>"): Ditto.
+	(define_expand "<avx512>_cvtmask2<ssemodesuffix><VI48_AVX512VL:mode>"): Ditto.
+	(define_insn "*<avx512>_cvtmask2<ssemodesuffix><VI48_AVX512VL:mode>"): Ditto.
+
 2014-10-15  Renlin Li <renlin.li@arm.com>
 
 	* config/aarch64/aarch64.h (ARM_DEFAULT_PCS, arm_pcs_variant): Delete.
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 690bed5..9566884 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -618,6 +618,15 @@
   return op == CONST0_RTX (mode);
 })
 
+;; Match -1.
+(define_predicate "constm1_operand"
+  (match_code "const_int,const_double,const_vector")
+{
+  if (mode == VOIDmode)
+    mode = GET_MODE (op);
+  return op == CONSTM1_RTX (mode);
+})
+
 ;; Match one or vector filled with ones.
 (define_predicate "const1_operand"
   (match_code "const_int,const_double,const_vector")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index fa2babf..018702a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -135,6 +135,7 @@
   UNSPEC_PMADDWD512
   UNSPEC_PSHUFHW
   UNSPEC_PSHUFLW
+  UNSPEC_CVTINT2MASK
 
   ;; For AVX512DQ support
   UNSPEC_REDUCE
@@ -4960,6 +4961,72 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "V8DF")])
 
+(define_insn "<avx512>_cvt<ssemodesuffix>2mask<mode>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+	(unspec:<avx512fmaskmode>
+	 [(match_operand:VI12_AVX512VL 1 "register_operand" "v")]
+	 UNSPEC_CVTINT2MASK))]
+  "TARGET_AVX512BW"
+  "vpmov<ssemodesuffix>2m\t{%1, %0|%0, %1}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<avx512>_cvt<ssemodesuffix>2mask<mode>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+	(unspec:<avx512fmaskmode>
+	 [(match_operand:VI48_AVX512VL 1 "register_operand" "v")]
+	 UNSPEC_CVTINT2MASK))]
+  "TARGET_AVX512DQ"
+  "vpmov<ssemodesuffix>2m\t{%1, %0|%0, %1}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "<avx512>_cvtmask2<ssemodesuffix><mode>"
+  [(set (match_operand:VI12_AVX512VL 0 "register_operand")
+	(vec_merge:VI12_AVX512VL
+	  (match_dup 2)
+	  (match_dup 3)
+	  (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+  "TARGET_AVX512BW"
+  {
+    operands[2] = CONSTM1_RTX (<MODE>mode);
+    operands[3] = CONST0_RTX (<MODE>mode);
+  })
+
+(define_insn "*<avx512>_cvtmask2<ssemodesuffix><mode>"
+  [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
+	(vec_merge:VI12_AVX512VL
+	  (match_operand:VI12_AVX512VL 2 "constm1_operand")
+	  (match_operand:VI12_AVX512VL 3 "const0_operand")
+	  (match_operand:<avx512fmaskmode> 1 "register_operand" "Yk")))]
+  "TARGET_AVX512BW"
+  "vpmovm2<ssemodesuffix>\t{%1, %0|%0, %1}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "<avx512>_cvtmask2<ssemodesuffix><mode>"
+  [(set (match_operand:VI48_AVX512VL 0 "register_operand")
+	(vec_merge:VI48_AVX512VL
+	  (match_dup 2)
+	  (match_dup 3)
+	  (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+  "TARGET_AVX512DQ"
+  "{
+    operands[2] = CONSTM1_RTX (<MODE>mode);
+    operands[3] = CONST0_RTX (<MODE>mode);
+  }")
+
+(define_insn "*<avx512>_cvtmask2<ssemodesuffix><mode>"
+  [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+	(vec_merge:VI48_AVX512VL
+	  (match_operand:VI48_AVX512VL 2 "constm1_operand")
+	  (match_operand:VI48_AVX512VL 3 "const0_operand")
+	  (match_operand:<avx512fmaskmode> 1 "register_operand" "Yk")))]
+  "TARGET_AVX512DQ"
+  "vpmovm2<ssemodesuffix>\t{%1, %0|%0, %1}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
 (define_insn "sse2_cvtps2pd<mask_name>"
   [(set (match_operand:V2DF 0 "register_operand" "=v")
 	(float_extend:V2DF