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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2014-11-24 18:58:40 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2014-11-24 18:58:40 +0000 |
| commit | 22186565977181492c37750e44571a54363d2624 (patch) | |
| tree | f9bcc515328cb1eaba9c73b4ac549f5b43d7b575 /gcc | |
| parent | d9d8d4e53f6c82a64ef38ddf899a7419d099b59e (diff) | |
| download | gcc-22186565977181492c37750e44571a54363d2624.zip gcc-22186565977181492c37750e44571a54363d2624.tar.gz gcc-22186565977181492c37750e44571a54363d2624.tar.bz2 | |
re PR target/63965 (ICE: in extract_constrain_insn, at recog.c:2230 on ppc64)
2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000-cpus.def: Undo November 21st changes, a
work in progress patch was committed instead of the fixes for
63965.
* config/rs6000/rs6000.c: Likewise.
From-SVN: r218027
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-cpus.def | 9 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 7 |
3 files changed, 19 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1ed780c..5df9ef6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/63965 + * config/rs6000/rs6000-cpus.def: Undo November 21st changes, a + work in progress patch was committed instead of the fixes for + 63965. + * config/rs6000/rs6000.c: Likewise. + 2014-11-22 Jan Hubicka <hubicka@ucw.cz> PR ipa/63671 diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 7bd5891..c1a7649 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -38,14 +38,14 @@ /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but altivec is a win so enable it. */ + /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until + PR 58587 is fixed. */ #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ | OPTION_MASK_POPCNTD \ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX \ - | OPTION_MASK_UPPER_REGS_DF \ - | OPTION_MASK_VSX_TIMODE) - + | OPTION_MASK_UPPER_REGS_DF) /* For now, don't provide an embedded version of ISA 2.07. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ @@ -188,8 +188,7 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD - | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF - | OPTION_MASK_VSX_TIMODE) + | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6d128c1..ea3e511 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7730,6 +7730,13 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) && legitimate_constant_pool_address_p (x, mode, reg_ok_strict || lra_in_progress)) return 1; + /* For TImode, if we have load/store quad and TImode in VSX registers, only + allow register indirect addresses. This will allow the values to go in + either GPRs or VSX registers without reloading. The vector types would + tend to go into VSX registers, so we allow REG+REG, while TImode seems + somewhat split, in that some uses are GPR based, and some VSX based. */ + if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE) + return 0; /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ if (! reg_ok_strict && reg_offset_p |