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authorBob Wilson <bob.wilson@acm.org>2008-08-29 04:34:15 +0000
committerBob Wilson <bwilson@gcc.gnu.org>2008-08-29 04:34:15 +0000
commit1d29a58dd0f00732090d5870f6286f583f9dbd39 (patch)
treeb668ee297ef3923bd0fb0f89a4fca9a0573b4e81 /gcc
parentd215563273a278f47422b33cbb1176027838cefb (diff)
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* config/xtensa/xtensa.md (<u>mulsidi3): Use a temporary register.
From-SVN: r139750
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/xtensa/xtensa.md5
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 753422f..1fd3468 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2008-08-28 Bob Wilson <bob.wilson@acm.org>
+
+ * config/xtensa/xtensa.md (<u>mulsidi3): Use a temporary register.
+
2008-08-28 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.h (ISA_HAS_BBIT): New macro.
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 7d85956b..cffbcd1 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -222,10 +222,11 @@
(any_extend:DI (match_operand:SI 2 "register_operand"))))]
"TARGET_MUL32_HIGH"
{
- emit_insn (gen_mulsi3 (gen_lowpart (SImode, operands[0]),
- operands[1], operands[2]));
+ rtx temp = gen_reg_rtx (SImode);
+ emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
operands[1], operands[2]));
+ emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp));
DONE;
})