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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2016-09-01 14:43:55 +0000 |
|---|---|---|
| committer | William Schmidt <wschmidt@gcc.gnu.org> | 2016-09-01 14:43:55 +0000 |
| commit | 1ca94f3674693ee3fa656a2f8c560f3bb8aa4a6e (patch) | |
| tree | e22b92f2589ee7abe2232371b29b35a4ac90bfec /gcc | |
| parent | 2a99de7b1ebe7b38e756dc736b59a684a8d87e1d (diff) | |
| download | gcc-1ca94f3674693ee3fa656a2f8c560f3bb8aa4a6e.zip gcc-1ca94f3674693ee3fa656a2f8c560f3bb8aa4a6e.tar.gz gcc-1ca94f3674693ee3fa656a2f8c560f3bb8aa4a6e.tar.bz2 | |
re PR target/72827 (gnat bootstrap broken on powerpc64le-linux-gnu)
2016-09-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/72827
* config/rs6000/rs6000.c (rs6000_legitimize_address): Avoid
reg+reg addressing for TImode.
(rs6000_legitimate_address_p): Only allow register indirect
addressing for TImode, even without TARGET_QUAD_MEMORY.
Co-Authored-By: Michael Meissner <meissner@linux.vnet.ibm.com>
From-SVN: r239938
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 16 |
2 files changed, 19 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c18752b..53335d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-09-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/72827 + * config/rs6000/rs6000.c (rs6000_legitimize_address): Avoid + reg+reg addressing for TImode. + (rs6000_legitimate_address_p): Only allow register indirect + addressing for TImode, even without TARGET_QUAD_MEMORY. + 2016-09-01 Richard Biener <rguenther@suse.de> PR middle-end/77436 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 2f15a05..557009f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -8409,7 +8409,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, pointer, so it works with both GPRs and VSX registers. */ /* Make sure both operands are registers. */ else if (GET_CODE (x) == PLUS - && (mode != TImode || !TARGET_QUAD_MEMORY)) + && (mode != TImode || !TARGET_VSX_TIMODE)) return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), force_reg (Pmode, XEXP (x, 1))); @@ -9418,12 +9418,16 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) return 1; } - /* For TImode, if we have load/store quad and TImode in VSX registers, only - allow register indirect addresses. This will allow the values to go in - either GPRs or VSX registers without reloading. The vector types would - tend to go into VSX registers, so we allow REG+REG, while TImode seems + /* For TImode, if we have TImode in VSX registers, only allow register + indirect addresses. This will allow the values to go in either GPRs + or VSX registers without reloading. The vector types would tend to + go into VSX registers, so we allow REG+REG, while TImode seems somewhat split, in that some uses are GPR based, and some VSX based. */ - if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE) + /* FIXME: We could loosen this by changing the following to + if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE) + but currently we cannot allow REG+REG addressing for TImode. See + PR72827 for complete details on how this ends up hoodwinking DSE. */ + if (mode == TImode && TARGET_VSX_TIMODE) return 0; /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ if (! reg_ok_strict |