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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-07-06 08:25:26 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-07-06 08:25:26 +0000 |
| commit | 193bee751a607fac9d85e0ce8e6462fb5de1b515 (patch) | |
| tree | 29d451e2a37afdb7995871adbe927a69b01a7a49 /gcc | |
| parent | 1f52d1a8b52ace2922eb9b97e2c49d2ee7d27410 (diff) | |
| download | gcc-193bee751a607fac9d85e0ce8e6462fb5de1b515.zip gcc-193bee751a607fac9d85e0ce8e6462fb5de1b515.tar.gz gcc-193bee751a607fac9d85e0ce8e6462fb5de1b515.tar.bz2 | |
[arm] Fix ambiguous .md attribute uses
This patch is part of a series that fixes ambiguous attribute
uses in .md files, i.e. cases in which attributes didn't use
<ITER:ATTR> to specify an iterator, and in which <ATTR> could
have different values depending on the iterator chosen.
I think this is a genuine bugfix for Thumb-1, since previously the
LDREX width was taken from the SImode success result rather than the
memory mode:
-#define HAVE_atomic_compare_and_swapt1qi_1 ((TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1))
-#define HAVE_atomic_compare_and_swapt1hi_1 ((TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1))
-#define HAVE_atomic_compare_and_swapt1di_1 ((TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1))
+#define HAVE_atomic_compare_and_swapt1qi_1 ((TARGET_HAVE_LDREXBH && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1))
+#define HAVE_atomic_compare_and_swapt1hi_1 ((TARGET_HAVE_LDREXBH && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1))
+#define HAVE_atomic_compare_and_swapt1di_1 ((TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN \
+ && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1))
The same goes for the predicate and constraints in
@atomic_compare_and_swapt1di_1, which previously used the
SI values from the success result.
2019-07-06 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/arm/sync.md
(@atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): Use
<NARROW:sync_predtab> instead of (implicitly) <CCSI:sync_predtab>.
(@atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise
<SIDI:sync_predtab>. Use <SIDI:cas_cmp_operand> and
<SIDI:cas_cmp_str>.
From-SVN: r273158
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/arm/sync.md | 6 |
2 files changed, 12 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3ce8b90..1ae6b1c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2019-07-06 Richard Sandiford <richard.sandiford@arm.com> + + * config/arm/sync.md + (@atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): Use + <NARROW:sync_predtab> instead of (implicitly) <CCSI:sync_predtab>. + (@atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise + <SIDI:sync_predtab>. Use <SIDI:cas_cmp_operand> and + <SIDI:cas_cmp_str>. + 2019-07-06 Jakub Jelinek <jakub@redhat.com> * omp-low.c (struct omp_context): Add for_simd_scan_phase member. diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 3d49aef..ed857d6 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -201,7 +201,7 @@ (match_operand:SI 7 "const_int_operand")] ;; mod_f VUNSPEC_ATOMIC_CAS)) (clobber (match_scratch:SI 8 "=&r,X,X,X"))] - "<sync_predtab>" + "<NARROW:sync_predtab>" "#" "&& reload_completed" [(const_int 0)] @@ -225,14 +225,14 @@ (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2) (unspec_volatile:SIDI - [(match_operand:SIDI 3 "<cas_cmp_operand>" "<cas_cmp_str>,lIL*h,J,*r") ;; expect + [(match_operand:SIDI 3 "<SIDI:cas_cmp_operand>" "<SIDI:cas_cmp_str>,lIL*h,J,*r") ;; expect (match_operand:SIDI 4 "s_register_operand" "r,r,r,r") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f VUNSPEC_ATOMIC_CAS)) (clobber (match_scratch:SI 8 "=&r,X,X,X"))] - "<sync_predtab>" + "<SIDI:sync_predtab>" "#" "&& reload_completed" [(const_int 0)] |