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author | Ralf Wildenhues <Ralf.Wildenhues@gmx.de> | 2009-12-15 18:33:16 +0000 |
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committer | Ralf Wildenhues <rwild@gcc.gnu.org> | 2009-12-15 18:33:16 +0000 |
commit | 1588fb31f6f7b46532ca18a3cc2cb8e9bd25c71e (patch) | |
tree | ad34821f8a36e7eae09d237ca6bf11e26b57d115 /gcc | |
parent | ec903a9c42e640af51c771cb3a844283acdc566b (diff) | |
download | gcc-1588fb31f6f7b46532ca18a3cc2cb8e9bd25c71e.zip gcc-1588fb31f6f7b46532ca18a3cc2cb8e9bd25c71e.tar.gz gcc-1588fb31f6f7b46532ca18a3cc2cb8e9bd25c71e.tar.bz2 |
Fix @itemx vs. @itemx
gcc/:
* doc/c-tree.texi (Expression trees): Use @itemx for all but
the first item for merged items.
* doc/extend.texi (Variable Attributes): Likewise.
* doc/install.texi (Configuration): Likewise.
* doc/invoke.texi (RS/6000 and PowerPC Options, RX Options):
Likewise.
From-SVN: r155263
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 9 | ||||
-rw-r--r-- | gcc/doc/c-tree.texi | 12 | ||||
-rw-r--r-- | gcc/doc/extend.texi | 8 | ||||
-rw-r--r-- | gcc/doc/install.texi | 2 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 6 |
5 files changed, 23 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b205823..3f424e6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2009-12-15 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> + + * doc/c-tree.texi (Expression trees): Use @itemx for all but + the first item for merged items. + * doc/extend.texi (Variable Attributes): Likewise. + * doc/install.texi (Configuration): Likewise. + * doc/invoke.texi (RS/6000 and PowerPC Options, RX Options): + Likewise. + 2009-12-15 Richard Guenther <rguenther@suse.de> * tree.c (free_lang_data_in_binfo): Do not free BINFO_OFFSET diff --git a/gcc/doc/c-tree.texi b/gcc/doc/c-tree.texi index 3549858..b53f758 100644 --- a/gcc/doc/c-tree.texi +++ b/gcc/doc/c-tree.texi @@ -2871,7 +2871,7 @@ chained together. This facilitates adding new clauses during compilation. @item VEC_LSHIFT_EXPR -@item VEC_RSHIFT_EXPR +@itemx VEC_RSHIFT_EXPR These nodes represent whole vector left and right shifts, respectively. The first operand is the vector to shift; it will always be of vector type. The second operand is an expression for the number of bits by which to @@ -2879,7 +2879,7 @@ shift. Note that the result is undefined if the second operand is larger than or equal to the first operand's type size. @item VEC_WIDEN_MULT_HI_EXPR -@item VEC_WIDEN_MULT_LO_EXPR +@itemx VEC_WIDEN_MULT_LO_EXPR These nodes represent widening vector multiplication of the high and low parts of the two input vectors, respectively. Their operands are vectors that contain the same number of elements (@code{N}) of the same integral type. @@ -2891,7 +2891,7 @@ low @code{N/2} elements of the two vector are multiplied to produce the vector of @code{N/2} products. @item VEC_UNPACK_HI_EXPR -@item VEC_UNPACK_LO_EXPR +@itemx VEC_UNPACK_LO_EXPR These nodes represent unpacking of the high and low parts of the input vector, respectively. The single operand is a vector that contains @code{N} elements of the same integral or floating point type. The result is a vector @@ -2902,7 +2902,7 @@ In the case of @code{VEC_UNPACK_LO_EXPR} the low @code{N/2} elements of the vector are extracted and widened (promoted). @item VEC_UNPACK_FLOAT_HI_EXPR -@item VEC_UNPACK_FLOAT_LO_EXPR +@itemx VEC_UNPACK_FLOAT_LO_EXPR These nodes represent unpacking of the high and low parts of the input vector, where the values are converted from fixed point to floating point. The single operand is a vector that contains @code{N} elements of the same @@ -2938,13 +2938,13 @@ elements of the two vectors are merged (concatenated) to form the output vector. @item VEC_EXTRACT_EVEN_EXPR -@item VEC_EXTRACT_ODD_EXPR +@itemx VEC_EXTRACT_ODD_EXPR These nodes represent extracting of the even/odd elements of the two input vectors, respectively. Their operands and result are vectors that contain the same number of elements of the same type. @item VEC_INTERLEAVE_HIGH_EXPR -@item VEC_INTERLEAVE_LOW_EXPR +@itemx VEC_INTERLEAVE_LOW_EXPR These nodes represent merging and interleaving of the high/low elements of the two input vectors, respectively. The operands and the result are vectors that contain the same number of elements (@code{N}) of the same type. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index dd5a89c..148185a 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -4235,8 +4235,8 @@ Three attributes are currently defined for the Blackfin. @table @code @item l1_data -@item l1_data_A -@item l1_data_B +@itemx l1_data_A +@itemx l1_data_B @cindex @code{l1_data} variable attribute @cindex @code{l1_data_A} variable attribute @cindex @code{l1_data_B} variable attribute @@ -4308,7 +4308,7 @@ allows modules to make no assumptions about where variables might be stored. @item io -@item io (@var{addr}) +@itemx io (@var{addr}) Variables with the @code{io} attribute are used to address memory-mapped peripherals. If an address is specified, the variable is assigned that address, else it is not assigned an address (it is @@ -4319,7 +4319,7 @@ int timer_count __attribute__((io(0x123))); @end example @item cb -@item cb (@var{addr}) +@itemx cb (@var{addr}) Variables with the @code{cb} attribute are used to access the control bus, using special instructions. @code{addr} indicates the control bus address. Example: diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 977aa80..b5bf1fd 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1432,7 +1432,7 @@ increase the risk of undetected internal errors causing wrong code to be generated. @item --disable-stage1-checking -@item --enable-stage1-checking +@itemx --enable-stage1-checking @itemx --enable-stage1-checking=@var{list} If no @option{--enable-checking} option is specified the stage1 compiler will be built with @samp{yes} checking enabled, otherwise diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b548d0c..5cfd378 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15072,7 +15072,7 @@ stored, which means code that walks the stack frame across interrupts or signals may get corrupted data. @item -mavoid-indexed-addresses -@item -mno-avoid-indexed-addresses +@itemx -mno-avoid-indexed-addresses @opindex mavoid-indexed-addresses @opindex mno-avoid-indexed-addresses Generate code that tries to avoid (not avoid) the use of indexed load @@ -15543,14 +15543,14 @@ experiment and discover whether this feature is of benefit to their program. @item -msim -@item -mno-sim +@itemx -mno-sim @opindex msim @opindex mno-sim Use the simulator runtime. The default is to use the libgloss board specific runtime. @item -mas100-syntax -@item -mno-as100-syntax +@itemx -mno-as100-syntax @opindex mas100-syntax @opindex mno-as100-syntax When generating assembler output use a syntax that is compatible with |