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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2014-11-21 12:29:26 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2014-11-21 12:29:26 +0000 |
| commit | 130ee2ebe76f52210bc81ebb44318300b59a6712 (patch) | |
| tree | 869e03ca84ba46f419c5982ecfd775fdce028833 /gcc | |
| parent | ba483b00de68c9d5dfca8de0789aa66dd3433d10 (diff) | |
| download | gcc-130ee2ebe76f52210bc81ebb44318300b59a6712.zip gcc-130ee2ebe76f52210bc81ebb44318300b59a6712.tar.gz gcc-130ee2ebe76f52210bc81ebb44318300b59a6712.tar.bz2 | |
[AArch64, Obvious] Fix formatting of SHLL and friends
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>): Add a tab between
output mnemonic and operands.
(aarch64_simd_vec_unpack<su>_lo_<mode>): Likewise.
(aarch64_simd_vec_unpack<su>_hi_<mode>): Likewise.
From-SVN: r217917
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 6 |
2 files changed, 11 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index af6add1..768b396 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2014-11-21 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>): Add a tab between + output mnemonic and operands. + (aarch64_simd_vec_unpack<su>_lo_<mode>): Likewise. + (aarch64_simd_vec_unpack<su>_hi_<mode>): Likewise. + 2014-11-21 Evgeny Stupachenko <evstupac@gmail.com> * config/i386/i386.c (ix86_option_override_internal): Increase diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 23345b1..926eb76 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1175,7 +1175,7 @@ (match_operand:VQW 2 "vect_par_cnst_lo_half" "") )))] "TARGET_SIMD" - "<su>shll %0.<Vwtype>, %1.<Vhalftype>, 0" + "<su>shll\t%0.<Vwtype>, %1.<Vhalftype>, 0" [(set_attr "type" "neon_shift_imm_long")] ) @@ -1186,7 +1186,7 @@ (match_operand:VQW 2 "vect_par_cnst_hi_half" "") )))] "TARGET_SIMD" - "<su>shll2 %0.<Vwtype>, %1.<Vtype>, 0" + "<su>shll2\t%0.<Vwtype>, %1.<Vtype>, 0" [(set_attr "type" "neon_shift_imm_long")] ) @@ -2601,7 +2601,7 @@ (ANY_EXTEND:<VWIDE> (match_operand:VDW 2 "register_operand" "w"))))] "TARGET_SIMD" - "<ANY_EXTEND:su><ADDSUB:optab>l %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + "<ANY_EXTEND:su><ADDSUB:optab>l\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" [(set_attr "type" "neon_<ADDSUB:optab>_long")] ) |