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| author | liuhongt <hongtao.liu@intel.com> | 2020-08-24 20:52:20 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2020-08-25 13:41:07 +0800 |
| commit | 108477875f01798eecd7780207396b8c44930ae9 (patch) | |
| tree | 3dd62f3356e0e6c16eddb6fef740bf4f52457a6e /gcc | |
| parent | bb5e895245ebef488b63efc239f64488aef65cf1 (diff) | |
| download | gcc-108477875f01798eecd7780207396b8c44930ae9.zip gcc-108477875f01798eecd7780207396b8c44930ae9.tar.gz gcc-108477875f01798eecd7780207396b8c44930ae9.tar.bz2 | |
Refine typo to fix ICE.
2020-08-24 Hongtao Liu <hongtao.liu@intel.com>
gcc/ChangeLog:
PR target/96755
* config/i386/sse.md: Correct the mode of NOT operands to
SImode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr96755.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/sse.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr96755.c | 16 |
2 files changed, 17 insertions, 1 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6f1f7f7..380dc45 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1588,7 +1588,7 @@ (define_split [(set (match_operand:DI 0 "mask_reg_operand") (zero_extend:DI - (not:DI (match_operand:SI 1 "mask_reg_operand"))))] + (not:SI (match_operand:SI 1 "mask_reg_operand"))))] "TARGET_AVX512BW && reload_completed" [(parallel [(set (match_dup 0) diff --git a/gcc/testsuite/gcc.target/i386/pr96755.c b/gcc/testsuite/gcc.target/i386/pr96755.c new file mode 100644 index 0000000..20fed58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr96755.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=skylake-avx512" } */ + +extern long var_22; +extern int arr_3[]; +extern int arr_4[][20][9]; +short a; +void test(unsigned short b, unsigned char e, long long g) { + for (long c = 0; c < 20ULL; c = g) + for (short d = 0; d < 9; d++) + for (char f = e; f < 8; f += 4) { + arr_3[f] = 0; + var_22 = ~(unsigned)b; + arr_4[c][d][f] = a; + } +} |