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| author | Adam Nemet <anemet@caviumnetworks.com> | 2009-01-12 04:27:31 +0000 |
|---|---|---|
| committer | Adam Nemet <nemet@gcc.gnu.org> | 2009-01-12 04:27:31 +0000 |
| commit | 0e510b3e4e3a6998f65b33b7f5b238abed2587d1 (patch) | |
| tree | 67732e4ff9b8d58f808ca86f7a12b76fd78f273b /gcc | |
| parent | 3f429b87549884dd2d649503b311baa8510c511a (diff) | |
| download | gcc-0e510b3e4e3a6998f65b33b7f5b238abed2587d1.zip gcc-0e510b3e4e3a6998f65b33b7f5b238abed2587d1.tar.gz gcc-0e510b3e4e3a6998f65b33b7f5b238abed2587d1.tar.bz2 | |
expmed.c (store_bit_field_1): Properly truncate the paradoxical subreg of op0 to the original op0.
* expmed.c (store_bit_field_1): Properly truncate the paradoxical
subreg of op0 to the original op0.
testsuite/
* gcc.target/mips/ins-2.c: New test.
From-SVN: r143288
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/expmed.c | 10 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/ins-2.c | 27 |
4 files changed, 46 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 28a86bc..ba53e7d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2009-01-11 Adam Nemet <anemet@caviumnetworks.com> + + * expmed.c (store_bit_field_1): Properly truncate the paradoxical + subreg of op0 to the original op0. + 2009-01-11 Laurent GUERBY <laurent@guerby.net> * doc/sourcebuild.texi (Source Tree): Move up intl and fixinc. diff --git a/gcc/expmed.c b/gcc/expmed.c index 50eb45f..9ee5f29 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -749,6 +749,16 @@ store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, if (pat) { emit_insn (pat); + + /* If the mode of the insertion is wider than the mode of the + target register we created a paradoxical subreg for the + target. Truncate the paradoxical subreg of the target to + itself properly. */ + if (!TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (op0)), + GET_MODE_BITSIZE (op_mode)) + && (REG_P (xop0) + || GET_CODE (xop0) == SUBREG)) + convert_move (op0, xop0, true); return true; } delete_insns_since (last); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 289a330..41f53a9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2009-01-11 Adam Nemet <anemet@caviumnetworks.com> + + * gcc.target/mips/ins-2.c: New test. + 2009-01-11 H.J. Lu <hongjiu.lu@intel.com> PR testsuite/38809 diff --git a/gcc/testsuite/gcc.target/mips/ins-2.c b/gcc/testsuite/gcc.target/mips/ins-2.c new file mode 100644 index 0000000..a71e6c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/ins-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O -meb isa_rev>=2 -mgp64" } */ +/* { dg-final { scan-assembler-times "\tins\t|\tdins\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tsll\t|\tins\t" 1 } } */ + +/* When inserting something into the top bit of a 32-bit structure, + we must make sure that the register remains properly sign-extended. + There are two ways of doing this: + + - use purely 32-bit bit manipulations (a single INS, matched twice here). + - use a 64-bit bit manipulation (DINS), and sign-extend the result. We + check for this extension using SLL. */ + +struct s +{ + int a:3; + int b:29; +}; + +NOMIPS16 void +f (int a) +{ + struct s s; + asm volatile ("" : "=r"(s)); + s.a = a; + asm volatile ("" :: "r"(s)); +} |