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| author | Dominik Infuehr <dominik.infuehr@theobroma-systems.com> | 2017-10-30 18:35:32 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2017-10-30 18:35:32 +0000 |
| commit | 0d1cf53834bdcbe23c20c872036754c028caaa06 (patch) | |
| tree | 8f123a1aec882825e9ab0ddea37c4279e7a0b2b2 /gcc | |
| parent | daff6cdf8ea49dd3a9fbb9120f4b5ef39fe78a9a (diff) | |
| download | gcc-0d1cf53834bdcbe23c20c872036754c028caaa06.zip gcc-0d1cf53834bdcbe23c20c872036754c028caaa06.tar.gz gcc-0d1cf53834bdcbe23c20c872036754c028caaa06.tar.bz2 | |
Wrong type-attribute for stp and str
Fix the type attributes of the integer stores in aarch64_simd_mov.
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Rename
both identically named patterns to (*aarch64_simd_mov<VD:mode>)
and (*aarch64_simd_mov<VQ:mode>).
(*aarch64_simd_mov<VD:mode>): Change type attribute to match
pattern alternative.
(*aarch64_simd_mov<VQ:mode>): Re-order and change type
attributes to match pattern alternative.
From-SVN: r254236
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 10 |
2 files changed, 15 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 380ae33..bfd68e9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-10-30 Dominik Infuehr <dominik.infuehr@theobroma-systems.com> + + * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Rename + both identically named patterns to (*aarch64_simd_mov<VD:mode>) + and (*aarch64_simd_mov<VQ:mode>). + (*aarch64_simd_mov<VD:mode>): Change type attribute to match + pattern alternative. + (*aarch64_simd_mov<VQ:mode>): Re-order and change type + attributes to match pattern alternative. + 2017-10-30 Steven Munroe <munroesj@gcc.gnu.org> * config.gcc (powerpc*-*-*): Add emmintrin.h. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 49f615c..447ee3a 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -102,7 +102,7 @@ [(set_attr "type" "neon_dup<q>")] ) -(define_insn "*aarch64_simd_mov<mode>" +(define_insn "*aarch64_simd_mov<VD:mode>" [(set (match_operand:VD 0 "nonimmediate_operand" "=w, m, m, w, ?r, ?w, ?r, w") (match_operand:VD 1 "general_operand" @@ -126,12 +126,12 @@ default: gcc_unreachable (); } } - [(set_attr "type" "neon_load1_1reg<q>, neon_stp, neon_store1_1reg<q>,\ + [(set_attr "type" "neon_load1_1reg<q>, store_8, neon_store1_1reg<q>,\ neon_logic<q>, neon_to_gp<q>, f_mcr,\ mov_reg, neon_move<q>")] ) -(define_insn "*aarch64_simd_mov<mode>" +(define_insn "*aarch64_simd_mov<VQ:mode>" [(set (match_operand:VQ 0 "nonimmediate_operand" "=w, Umq, m, w, ?r, ?w, ?r, w") (match_operand:VQ 1 "general_operand" @@ -160,8 +160,8 @@ gcc_unreachable (); } } - [(set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\ - neon_stp, neon_logic<q>, multiple, multiple,\ + [(set_attr "type" "neon_load1_1reg<q>, store_16, neon_store1_1reg<q>,\ + neon_logic<q>, multiple, multiple,\ multiple, neon_move<q>") (set_attr "length" "4,4,4,4,8,8,8,4")] ) |