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| author | Ian Bolton <ian.bolton@arm.com> | 2013-03-19 16:23:08 +0000 |
|---|---|---|
| committer | Ian Bolton <ibolton@gcc.gnu.org> | 2013-03-19 16:23:08 +0000 |
| commit | 0b8cdc58698e50c4842bbc297e0558ac8387af78 (patch) | |
| tree | 488ce34235fcbb435ab6b173dab3cadf55a3998c /gcc | |
| parent | 5977a10d4a600792417e439d7bc67a514226a125 (diff) | |
| download | gcc-0b8cdc58698e50c4842bbc297e0558ac8387af78.zip gcc-0b8cdc58698e50c4842bbc297e0558ac8387af78.tar.gz gcc-0b8cdc58698e50c4842bbc297e0558ac8387af78.tar.bz2 | |
AArch64 backend support for SBC instruction.
From-SVN: r196797
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 28 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 |
3 files changed, 37 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d55999e..b6ae43a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2013-03-19 Ian Bolton <ian.bolton@arm.com> + * config/aarch64/aarch64.md (*sub<mode>3_carryin): New pattern. + (*subsi3_carryin_uxtw): Likewise. + +2013-03-19 Ian Bolton <ian.bolton@arm.com> + * config/aarch64/aarch64.md (*ror<mode>3_insn): New pattern. (*rorsi3_insn_uxtw): Likewise. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4358b44..c99e188 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1790,6 +1790,34 @@ (set_attr "mode" "SI")] ) +(define_insn "*sub<mode>3_carryin" + [(set + (match_operand:GPI 0 "register_operand" "=r") + (minus:GPI (minus:GPI + (match_operand:GPI 1 "register_operand" "r") + (ltu:GPI (reg:CC CC_REGNUM) (const_int 0))) + (match_operand:GPI 2 "register_operand" "r")))] + "" + "sbc\\t%<w>0, %<w>1, %<w>2" + [(set_attr "v8type" "adc") + (set_attr "mode" "<MODE>")] +) + +;; zero_extend version of the above +(define_insn "*subsi3_carryin_uxtw" + [(set + (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (minus:SI (minus:SI + (match_operand:SI 1 "register_operand" "r") + (ltu:SI (reg:CC CC_REGNUM) (const_int 0))) + (match_operand:SI 2 "register_operand" "r"))))] + "" + "sbc\\t%w0, %w1, %w2" + [(set_attr "v8type" "adc") + (set_attr "mode" "SI")] +) + (define_insn "*sub_uxt<mode>_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "r") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e198a6e..6769ff7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2013-03-19 Ian Bolton <ian.bolton@arm.com> + * gcc.target/aarch64/sbc.c: New test. + +2013-03-19 Ian Bolton <ian.bolton@arm.com> + * gcc.target/aarch64/ror.c: New test. 2013-03-19 Ian Bolton <ian.bolton@arm.com> |