(cmpM_cc): Allow first operand to be a MEM.

Don't allow both operands to be MEM.
(float addM3,subM3,divM3,mulM3 recognizers): Don't allow either operand
to be a constant.
(all float patterns, FLOAT_EXTEND operands): Don't allow GENERAL_REGS
for float_extended operand.
(all float patterns, FLOAT operands): Change constraints to get better
register classification.
(fix_truncMN2 patterns): Likewise.
(floatMN2 patterns): Likewise.

From-SVN: r3296

1 files changed, 98 insertions, 60 deletions

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index e94af8f..9148d9e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -300,27 +300,46 @@
 
 (define_insn "cmpdf_cc"
   [(set (cc0)
+	(compare:CC (match_operand:DF 0 "nonimmediate_operand" "f,fm")
+		    (match_operand:DF 1 "nonimmediate_operand" "fm,f")))
+   (clobber (match_scratch:HI 2 "=a,a"))]
+  "TARGET_80387
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "* return (char *) output_float_compare (insn, operands);")
+
+(define_insn ""
+  [(set (cc0)
 	(compare:CC (match_operand:DF 0 "register_operand" "f")
-		    (match_operand:DF 1 "nonimmediate_operand" "fm")))
+		    (float:DF
+		     (match_operand:SI 1 "nonimmediate_operand" "rm"))))
    (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
   "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
-	(compare:CC (match_operand:DF 0 "register_operand" "f,f")
-		    (float:DF
-		     (match_operand:SI 1 "nonimmediate_operand" "m,!*r"))))
-   (clobber (match_scratch:HI 2 "=a,a"))]
+	(compare:CC (float:DF
+		     (match_operand:SI 0 "nonimmediate_operand" "rm"))
+		    (match_operand:DF 1 "register_operand" "f")))
+   (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
   "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
-	(compare:CC (match_operand:DF 0 "register_operand" "f,f")
+	(compare:CC (match_operand:DF 0 "register_operand" "f")
 		    (float_extend:DF
-		     (match_operand:SF 1 "nonimmediate_operand" "fm,!*r"))))
-   (clobber (match_scratch:HI 2 "=a,a"))]
+		     (match_operand:SF 1 "nonimmediate_operand" "fm"))))
+   (clobber (match_scratch:HI 2 "=a"))]
+  "TARGET_80387"
+  "* return (char *) output_float_compare (insn, operands);")
+
+(define_insn ""
+  [(set (cc0)
+	(compare:CC (float_extend:DF
+		     (match_operand:SF 0 "nonimmediate_operand" "fm"))
+		    (match_operand:DF 1 "register_operand" "f")))
+   (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
   "* return (char *) output_float_compare (insn, operands);")
 
@@ -341,20 +360,39 @@
   "TARGET_80387"
   "* return (char *) output_float_compare (insn, operands);")
 
+(define_insn ""
+  [(set (cc0)
+	(compare:CCFPEQ (float_extend:DF
+			 (match_operand:SF 0 "register_operand" "f"))
+			(match_operand:DF 1 "register_operand" "f")))
+   (clobber (match_scratch:HI 2 "=a"))]
+  "TARGET_80387"
+  "* return (char *) output_float_compare (insn, operands);")
+
 (define_insn "cmpsf_cc"
   [(set (cc0)
+	(compare:CC (match_operand:SF 0 "nonimmediate_operand" "f,fm")
+		    (match_operand:SF 1 "nonimmediate_operand" "fm,f")))
+   (clobber (match_scratch:HI 2 "=a,a"))]
+  "TARGET_80387
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "* return (char *) output_float_compare (insn, operands);")
+
+(define_insn ""
+  [(set (cc0)
 	(compare:CC (match_operand:SF 0 "register_operand" "f")
-		    (match_operand:SF 1 "nonimmediate_operand" "fm")))
+		    (float:SF
+		     (match_operand:SI 1 "nonimmediate_operand" "rm"))))
    (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
   "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
-	(compare:CC (match_operand:SF 0 "register_operand" "f,f")
-		    (float:SF
-		     (match_operand:SI 1 "nonimmediate_operand" "m,!*r"))))
-   (clobber (match_scratch:HI 2 "=a,a"))]
+	(compare:CC (float:SF
+		     (match_operand:SI 0 "nonimmediate_operand" "rm"))
+		    (match_operand:SF 1 "register_operand" "f")))
+   (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
   "* return (char *) output_float_compare (insn, operands);")
 
@@ -1253,17 +1291,17 @@
 ;; These match a signed conversion of either DFmode or SFmode to DImode.
 
 (define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=m,!*r")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f,f"))))
-   (clobber (match_scratch:HI 2 "=&r,&r"))
+  [(set (match_operand:DI 0 "general_operand" "=rm")
+	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
+   (clobber (match_scratch:HI 2 "=&r"))
    (clobber (match_dup 1))]
   "TARGET_80387"
   "* return (char *) output_fix_trunc (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=m,!*r")
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f,f"))))
-   (clobber (match_scratch:HI 2 "=&r,&r"))
+  [(set (match_operand:DI 0 "general_operand" "=rm")
+	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
+   (clobber (match_scratch:HI 2 "=&r"))
    (clobber (match_dup 1))]
   "TARGET_80387"
   "* return (char *) output_fix_trunc (insn, operands);")
@@ -1287,16 +1325,16 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=m,!*r")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f,f"))))
-   (clobber (match_scratch:HI 2 "=&r,&r"))]
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
+   (clobber (match_scratch:HI 2 "=&r"))]
   "TARGET_80387"
   "* return (char *) output_fix_trunc (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=m,!*r")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f,f"))))
-   (clobber (match_scratch:HI 2 "=&r,&r"))]
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
+   (clobber (match_scratch:HI 2 "=&r"))]
   "TARGET_80387"
   "* return (char *) output_fix_trunc (insn, operands);")
 
@@ -1307,33 +1345,33 @@
 
 (define_expand "floatsisf2"
   [(set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_operand:SI 1 "general_operand" "")))]
+	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
 (define_expand "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_operand:DI 1 "general_operand" "")))]
+	(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
 (define_expand "floatsidf2"
   [(set (match_operand:DF 0 "register_operand" "")
-	(float:DF (match_operand:SI 1 "general_operand" "")))]
+	(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
 (define_expand "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "")
-	(float:DF (match_operand:DI 1 "general_operand" "")))]
+	(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
 ;; This will convert from SImode or DImode to MODE_FLOAT.
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(float:DF (match_operand:DI 1 "general_operand" "m,!*r")))]
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float:DF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
   "TARGET_80387"
   "*
 {
@@ -1349,8 +1387,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(float:SF (match_operand:DI 1 "general_operand" "m,!*r")))]
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float:SF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
   "TARGET_80387"
   "*
 {
@@ -1366,8 +1404,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(float:DF (match_operand:SI 1 "general_operand" "m,!*r")))]
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
   "TARGET_80387"
   "*
 {
@@ -1383,8 +1421,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(float:SF (match_operand:SI 1 "general_operand" "m,!*r")))]
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
   "TARGET_80387"
   "*
 {
@@ -4223,65 +4261,65 @@
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_387_op"
-			[(match_operand:DF 1 "general_operand" "0,fm")
-			 (match_operand:DF 2 "general_operand" "fm,0")]))]
+			[(match_operand:DF 1 "nonimmediate_operand" "0,fm")
+			 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
+  [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 3 "binary_387_op"
-	   [(float:DF (match_operand:SI 1 "general_operand" "m,!*r"))
-	    (match_operand:DF 2 "general_operand" "0,0")]))]
+	   [(float:DF (match_operand:SI 1 "general_operand" "rm"))
+	    (match_operand:DF 2 "general_operand" "0")]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_387_op"
-	   [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,!*r,0"))
-	    (match_operand:DF 2 "general_operand" "0,0,f")]))]
+	   [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0"))
+	    (match_operand:DF 2 "general_operand" "0,f")]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
+  [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 3 "binary_387_op"
-	  [(match_operand:DF 1 "general_operand" "0,0")
-	   (float:DF (match_operand:SI 2 "general_operand" "m,!*r"))]))]
+	  [(match_operand:DF 1 "general_operand" "0")
+	   (float:DF (match_operand:SI 2 "general_operand" "rm"))]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_387_op"
-	  [(match_operand:DF 1 "general_operand" "0,0,f")
+	  [(match_operand:DF 1 "general_operand" "0,f")
 	   (float_extend:DF
-	    (match_operand:SF 2 "general_operand" "fm,!*r,0"))]))]
+	    (match_operand:SF 2 "general_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(match_operator:SF 3 "binary_387_op"
-			[(match_operand:SF 1 "general_operand" "0,fm")
-			 (match_operand:SF 2 "general_operand" "fm,0")]))]
+			[(match_operand:SF 1 "nonimmediate_operand" "0,fm")
+			 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
+  [(set (match_operand:SF 0 "register_operand" "=f")
 	(match_operator:SF 3 "binary_387_op"
-	  [(float:SF (match_operand:SI 1 "general_operand" "m,!*r"))
-	   (match_operand:SF 2 "general_operand" "0,0")]))]
+	  [(float:SF (match_operand:SI 1 "general_operand" "rm"))
+	   (match_operand:SF 2 "general_operand" "0")]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
+  [(set (match_operand:SF 0 "register_operand" "=f")
 	(match_operator:SF 3 "binary_387_op"
-	  [(match_operand:SF 1 "general_operand" "0,0")
-	   (float:SF (match_operand:SI 2 "general_operand" "m,!*r"))]))]
+	  [(match_operand:SF 1 "general_operand" "0")
+	   (float:SF (match_operand:SI 2 "general_operand" "rm"))]))]
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
@@ -4306,7 +4344,7 @@
 
 ;; It might seem that operands 0 & 1 could use predicate register_operand.
 ;; But strength reduction might offset the MEM expression.  So we let
-;; reload put the address into %edi & %esi.
+;; reload put the address into %edi.
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=&c")