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| author | Bernd Schmidt <bernds@codesourcery.com> | 2014-05-21 09:29:25 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@gcc.gnu.org> | 2014-05-21 09:29:25 +0000 |
| commit | 0836b77f3d4aa937d0a60dd292301a1021fa5272 (patch) | |
| tree | 5d0dd4cdb95c5fe6c625060a5675297c96ee4214 /gcc | |
| parent | 8a9e6b45baed602a208c6be551fd9708e1d06809 (diff) | |
| download | gcc-0836b77f3d4aa937d0a60dd292301a1021fa5272.zip gcc-0836b77f3d4aa937d0a60dd292301a1021fa5272.tar.gz gcc-0836b77f3d4aa937d0a60dd292301a1021fa5272.tar.bz2 | |
Make the Blackfin port build again.
* config/bfin/bfin.c (split_load_immediate): Use gen_int_mode in a few
more places.
From-SVN: r210684
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/config/bfin/bfin.c | 14 |
2 files changed, 12 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a80370b..ac95586 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2014-05-21 Bernd Schmidt <bernds@codesourcery.com> + * config/bfin/bfin.c (split_load_immediate): Use gen_int_mode in a few + more places. + * cfgrtl.c (cfg_layout_initialize): Weaken assert to only trigger if flag_reorder_blocks_and_partition. * hw-doloop.c (reorg_loops): Avoid reordering if that flag is set. diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index f860099..7945de4 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -2588,7 +2588,7 @@ split_load_immediate (rtx operands[]) && (D_REGNO_P (regno) || (regno >= REG_P0 && regno <= REG_P7 && num_zero <= 2))) { - emit_insn (gen_movsi (operands[0], GEN_INT (shifted))); + emit_insn (gen_movsi (operands[0], gen_int_mode (shifted, SImode))); emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_zero))); return 1; } @@ -2602,13 +2602,15 @@ split_load_immediate (rtx operands[]) if (log2constp (val & 0xFFFF0000)) { emit_insn (gen_movsi (operands[0], GEN_INT (val & 0xFFFF))); - emit_insn (gen_iorsi3 (operands[0], operands[0], GEN_INT (val & 0xFFFF0000))); + emit_insn (gen_iorsi3 (operands[0], operands[0], + gen_int_mode (val & 0xFFFF0000, SImode))); return 1; } else if (log2constp (val | 0xFFFF) && (val & 0x8000) != 0) { emit_insn (gen_movsi (operands[0], GEN_INT (tmp))); - emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (val | 0xFFFF))); + emit_insn (gen_andsi3 (operands[0], operands[0], + gen_int_mode (val | 0xFFFF, SImode))); } } @@ -2617,7 +2619,9 @@ split_load_immediate (rtx operands[]) if (tmp >= -64 && tmp <= 63) { emit_insn (gen_movsi (operands[0], GEN_INT (tmp))); - emit_insn (gen_movstricthi_high (operands[0], GEN_INT (val & -65536))); + emit_insn (gen_movstricthi_high (operands[0], + gen_int_mode (val & -65536, + SImode))); return 1; } @@ -2645,7 +2649,7 @@ split_load_immediate (rtx operands[]) { /* If optimizing for size, generate a sequence that has more instructions but is shorter. */ - emit_insn (gen_movsi (operands[0], GEN_INT (shifted_compl))); + emit_insn (gen_movsi (operands[0], gen_int_mode (shifted_compl, SImode))); emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_compl_zero))); emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); |