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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-11-01 20:47:28 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-11-01 20:47:28 +0000 |
| commit | ff1335e2080f16f9b42b9a886c8c063f869a6eed (patch) | |
| tree | 1c94e8a34c9825fdf1cfce0fab744f56fa0f55b4 /gcc | |
| parent | 0100c5f9b7d6e622d66bc90da0f2bfcdf9722d71 (diff) | |
| download | gcc-ff1335e2080f16f9b42b9a886c8c063f869a6eed.zip gcc-ff1335e2080f16f9b42b9a886c8c063f869a6eed.tar.gz gcc-ff1335e2080f16f9b42b9a886c8c063f869a6eed.tar.bz2 | |
[AArch64] Rename the internal "Upl" constraint
The SVE port uses the public constraints "Upl" and "Upa" to mean
"low predicate register" and "any predicate register" respectively.
"Upl" was already used as an internal-only constraint by the
addition patterns, so this patch renames it to "Uaa" ("two adds
needed").
2017-11-01 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/constraints.md (Upl): Rename to...
(Uaa): ...this.
* config/aarch64/aarch64.md
(*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
Update accordingly.
Reviewed-By: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254326
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/constraints.md | 2 |
3 files changed, 13 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fc88c85..98fc25e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,16 @@ Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> + * config/aarch64/constraints.md (Upl): Rename to... + (Uaa): ...this. + * config/aarch64/aarch64.md + (*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw): + Update accordingly. + +2017-11-01 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + * config/aarch64/aarch64.c (aarch64_add_constant_internal) (aarch64_add_constant, aarch64_add_sp, aarch64_sub_sp): Move earlier in file. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index bbd5174..ce75cf4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1562,7 +1562,7 @@ (match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r") (plus:GPI (match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk") - (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))] + (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa")))] "" "@ add\\t%<w>0, %<w>1, %2 @@ -1580,7 +1580,7 @@ (match_operand:DI 0 "register_operand" "=rk,rk,rk,r") (zero_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk") - (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))] + (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Uaa"))))] "" "@ add\\t%w0, %w1, %2 diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 77c510c..77ca85d 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -35,7 +35,7 @@ (and (match_code "const_int") (match_test "aarch64_uimm12_shift (ival)"))) -(define_constraint "Upl" +(define_constraint "Uaa" "@internal A constant that matches two uses of add instructions." (and (match_code "const_int") (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)"))) |