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| author | Jim Wilson <wilson@gcc.gnu.org> | 1993-04-06 12:36:49 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1993-04-06 12:36:49 -0700 |
| commit | fdd79c58a2938ccd78e94332a102e74865d2a964 (patch) | |
| tree | d16f84626c00660123289f788cc80bdc3f1ce328 /gcc | |
| parent | 8fad1c106d6c86458084e38ed5df27efe81b5ea1 (diff) | |
| download | gcc-fdd79c58a2938ccd78e94332a102e74865d2a964.zip gcc-fdd79c58a2938ccd78e94332a102e74865d2a964.tar.gz gcc-fdd79c58a2938ccd78e94332a102e74865d2a964.tar.bz2 | |
(lshldi3, lshrdi3): Define.
From-SVN: r4035
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index cf98d4d..12d75e3 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2532,6 +2532,46 @@ "" "sll %1,%2,%0") +(define_expand "lshldi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (lshift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "const_int_operand" ""))) + (clobber (match_scratch:SI 3 ""))])] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + FAIL; +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "const_int_operand" "I"))) + (clobber (match_scratch:SI 3 "=r"))] + "INTVAL (operands[2]) < 32" + "* +{ + operands[4] = GEN_INT (32 - INTVAL (operands[2])); + return \"srl %R1,%4,%3\;sll %R1,%2,%R0\;sll %1,%2,%0\;or %3,%0,%0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "4")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "const_int_operand" "I"))) + (clobber (match_scratch:SI 3 "=X"))] + "INTVAL (operands[2]) >= 32" + "* +{ + operands[4] = GEN_INT (INTVAL (operands[2]) - 32); + return \"sll %R1,%4,%0\;mov %%g0,%R0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "2")]) + (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") @@ -2545,6 +2585,46 @@ (match_operand:SI 2 "arith_operand" "rI")))] "" "srl %1,%2,%0") + +(define_expand "lshrdi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "const_int_operand" ""))) + (clobber (match_scratch:SI 3 ""))])] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + FAIL; +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "const_int_operand" "I"))) + (clobber (match_scratch:SI 3 "=r"))] + "INTVAL (operands[2]) < 32" + "* +{ + operands[4] = GEN_INT (32 - INTVAL (operands[2])); + return \"sll %1,%4,%3\;srl %1,%2,%0\;srl %R1,%2,%R0\;or %3,%R0,%R0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "4")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "const_int_operand" "I"))) + (clobber (match_scratch:SI 3 "=X"))] + "INTVAL (operands[2]) >= 32" + "* +{ + operands[4] = GEN_INT (INTVAL (operands[2]) - 32); + return \"srl %1,%4,%R0\;mov %%g0,%0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; Unconditional and other jump instructions ;; On the Sparc, by setting the annul bit on an unconditional branch, the |