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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-04-04 19:20:47 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-04-04 19:21:48 -0600 |
| commit | fdc5abbdcfb65d415af6c40230f8f07872e51e49 (patch) | |
| tree | fcc1169acc1a182fb0352c96b2d50e85f10921b4 /gcc | |
| parent | 4f81edad41caea4ddd269555f88790cec28cc9d9 (diff) | |
| download | gcc-fdc5abbdcfb65d415af6c40230f8f07872e51e49.zip gcc-fdc5abbdcfb65d415af6c40230f8f07872e51e49.tar.gz gcc-fdc5abbdcfb65d415af6c40230f8f07872e51e49.tar.bz2 | |
[PATCH] RISC-V: Fix PR109399 VSETVL PASS bug
PR 109399
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::compute_local_backward_infos): Update user vsetvl in local
demand fusion.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr109399.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c | 14 |
2 files changed, 21 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index b5f5301..1b66e3b 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2683,7 +2683,13 @@ pass_vsetvl::compute_local_backward_infos (const bb_info *bb) if (!(propagate_avl_across_demands_p (change, info) && !reg_available_p (insn, change)) && change.compatible_p (info)) - info = change.merge (info); + { + info = change.merge (info); + /* Fix PR109399, we should update user vsetvl instruction + if there is a change in demand fusion. */ + if (vsetvl_insn_p (insn->rtl ())) + change_vsetvl_insn (insn, info); + } } change = info; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c new file mode 100644 index 0000000..b3abad7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void foo(void *in1, void *in2, void *in3, void *out, size_t n) { + size_t vl = __riscv_vsetvlmax_e32m1(); + vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); + vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl); + vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl); + __riscv_vse32_v_i32m1(out, c, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ |