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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-07 04:07:53 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-07 04:07:53 +0000 |
| commit | f62a2af5dfaee45ae09bd170904daae80d822866 (patch) | |
| tree | 69c52ca1892921f706f90750a5d2692f71a11cff /gcc | |
| parent | e0617fb647400a1bd5400bd7205ce20f0d6efa13 (diff) | |
| download | gcc-f62a2af5dfaee45ae09bd170904daae80d822866.zip gcc-f62a2af5dfaee45ae09bd170904daae80d822866.tar.gz gcc-f62a2af5dfaee45ae09bd170904daae80d822866.tar.bz2 | |
[NDS32] Support [$ra + $rb << 3] form for load/store address.
gcc/
* config/nds32/nds32.c (nds32_legitimate_index_p): Modify condition
for load/store addressing form.
(nds32_print_operand_address): Likewise.
From-SVN: r259201
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.c | 14 |
2 files changed, 15 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f527374..d6c631c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-04-07 Chung-Ju Wu <jasonwucj@gmail.com> + + * config/nds32/nds32.c (nds32_legitimate_index_p): Modify condition + for load/store addressing form. + (nds32_print_operand_address): Likewise. + 2018-04-06 Eric Botcazou <ebotcazou@adacore.com> PR target/85196 diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index 030fb2e..b4c31a4 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -1246,9 +1246,10 @@ nds32_legitimate_index_p (machine_mode outer_mode, int multiplier; multiplier = INTVAL (op1); - /* We only allow (mult reg const_int_1) - or (mult reg const_int_2) or (mult reg const_int_4). */ - if (multiplier != 1 && multiplier != 2 && multiplier != 4) + /* We only allow (mult reg const_int_1), (mult reg const_int_2), + (mult reg const_int_4) or (mult reg const_int_8). */ + if (multiplier != 1 && multiplier != 2 + && multiplier != 4 && multiplier != 8) return false; regno = REGNO (op0); @@ -1273,8 +1274,9 @@ nds32_legitimate_index_p (machine_mode outer_mode, sv = INTVAL (op1); /* We only allow (ashift reg const_int_0) - or (ashift reg const_int_1) or (ashift reg const_int_2). */ - if (sv != 0 && sv != 1 && sv !=2) + or (ashift reg const_int_1) or (ashift reg const_int_2) or + (ashift reg const_int_3). */ + if (sv != 0 && sv != 1 && sv !=2 && sv != 3) return false; regno = REGNO (op0); @@ -2926,6 +2928,8 @@ nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) sv = 1; else if (INTVAL (XEXP (op0, 1)) == 4) sv = 2; + else if (INTVAL (XEXP (op0, 1)) == 8) + sv = 3; else gcc_unreachable (); |