aarch64: Add a %Z operand modifier for SVE registers

This patch adds a %Z operand modifier that prints registers as SVE z
registers.  The SME patches need this, but so do Tamar's patches.
I'm separating this out to unblock those.

We should probably document the [wxbhsdqZ] modifiers as
user-facing, but doing that for all of them is a separate patch.

gcc/
	* config/aarch64/aarch64.cc (aarch64_print_operand): Add a %Z
	modifier for SVE registers.

1 files changed, 6 insertions, 0 deletions

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index cb65ccc..968a9ac 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -12091,6 +12091,10 @@ sizetochar (int size)
      'N':		Take the duplicated element in a vector constant
 			and print the negative of it in decimal.
      'b/h/s/d/q':	Print a scalar FP/SIMD register name.
+     'Z':		Same for SVE registers.  ('z' was already taken.)
+			Note that it is not necessary to use %Z for operands
+			that have SVE modes.  The convention is to use %Z
+			only for non-SVE (or potentially non-SVE) modes.
      'S/T/U/V':		Print a FP/SIMD register name for a register list.
 			The register printed is the FP/SIMD register name
 			of X + 0/1/2/3 for S/T/U/V.
@@ -12263,6 +12267,8 @@ aarch64_print_operand (FILE *f, rtx x, int code)
     case 's':
     case 'd':
     case 'q':
+    case 'Z':
+      code = TOLOWER (code);
       if (!REG_P (x) || !FP_REGNUM_P (REGNO (x)))
 	{
 	  output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);