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authorBin Cheng <bin.cheng@arm.com>2016-05-23 14:44:07 +0000
committerBin Cheng <amker@gcc.gnu.org>2016-05-23 14:44:07 +0000
commitf397602394168dffc7a14cc116498549847098f9 (patch)
treea66e462485658cc06e3f5257aab53489dd34ef20 /gcc
parent18b5400419aa18463e605e53020b5186007d60b1 (diff)
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tree-ssa-address.c (copy_ref_info): Check NULL TMR_STEP when TMR_INDEX is non-NULL.
* tree-ssa-address.c (copy_ref_info): Check NULL TMR_STEP when TMR_INDEX is non-NULL. From-SVN: r236593
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/tree-ssa-address.c4
2 files changed, 9 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d85700a..311e632 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-05-23 Bin Cheng <bin.cheng@arm.com>
+
+ * tree-ssa-address.c (copy_ref_info): Check NULL TMR_STEP when
+ TMR_INDEX is non-NULL.
+
2016-05-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/71230
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 9e49f3d..b04545c 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -877,6 +877,10 @@ copy_ref_info (tree new_ref, tree old_ref)
&& TREE_CODE (old_ref) == MEM_REF
&& !(TREE_CODE (new_ref) == TARGET_MEM_REF
&& (TMR_INDEX2 (new_ref)
+ /* TODO: Below conditions can be relaxed if TMR_INDEX
+ is an indcution variable and its initial value and
+ step are aligned. */
+ || (TMR_INDEX (new_ref) && !TMR_STEP (new_ref))
|| (TMR_STEP (new_ref)
&& (TREE_INT_CST_LOW (TMR_STEP (new_ref))
< align)))))