diff options
| author | Alex Coplan <alex.coplan@arm.com> | 2023-12-15 09:32:42 +0000 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2023-12-15 09:35:45 +0000 |
| commit | ef9754dfdf18a89de3da23c4f23365f4c2611367 (patch) | |
| tree | e1c46cadb19a61f202ca6e36ee6ba022bc70dc03 /gcc | |
| parent | bac33a522bb51e30729191e935f25c2b0a63e225 (diff) | |
| download | gcc-ef9754dfdf18a89de3da23c4f23365f4c2611367.zip gcc-ef9754dfdf18a89de3da23c4f23365f4c2611367.tar.gz gcc-ef9754dfdf18a89de3da23c4f23365f4c2611367.tar.bz2 | |
aarch64: Handle autoinc addresses in ld1rq splitter [PR112906]
This patch uses the new force_reload_address routine added by the
previous patch to fix PR112906.
gcc/ChangeLog:
PR target/112906
* config/aarch64/aarch64-sve.md (@aarch64_vec_duplicate_vq<mode>_le):
Use force_reload_address to reload addresses that aren't suitable for
ld1rq in the pre-RA splitter.
gcc/testsuite/ChangeLog:
PR target/112906
* gcc.target/aarch64/sve/acle/general/pr112906.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr112906.c | 17 |
2 files changed, 18 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 32630db..27b945e 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2690,10 +2690,7 @@ { if (can_create_pseudo_p () && !aarch64_sve_ld1rq_operand (operands[1], <V128>mode)) - { - rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); - operands[1] = replace_equiv_address (operands[1], addr); - } + operands[1] = force_reload_address (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (VNx16BImode); emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode)); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr112906.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr112906.c new file mode 100644 index 0000000..69b653f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr112906.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2" } */ +#include <arm_sve.h> +unsigned c; +long d; +void f() { + unsigned char *b; + svbool_t x = svptrue_b8(); + svuint32_t g; + svuint8_t h, i; + d = 0; + for (; (unsigned *)d < &c; d += 16) { + h = svld1rq(x, &b[d]); + g = svdot_lane(g, i, h, 3); + } + svst1_vnum(x, &c, 8, g); +} |