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| author | Alexandre Oliva <aoliva@redhat.com> | 2000-12-01 02:03:24 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@gcc.gnu.org> | 2000-12-01 02:03:24 +0000 |
| commit | ecfdeaeb3445d0fd2fc9758f6deeb207bbb4b90d (patch) | |
| tree | a08f99604d8a8f3ed8ea92b695cb54d4536a6dbe /gcc | |
| parent | 6934615b9736d0a777ce7f6933129ea1cdd2dd23 (diff) | |
| download | gcc-ecfdeaeb3445d0fd2fc9758f6deeb207bbb4b90d.zip gcc-ecfdeaeb3445d0fd2fc9758f6deeb207bbb4b90d.tar.gz gcc-ecfdeaeb3445d0fd2fc9758f6deeb207bbb4b90d.tar.bz2 | |
sh.md (fpu_switch0, [...]): Only match on TARGET_SH4.
* config/sh/sh.md (fpu_switch0, fpu_switch1, movpsi, fpu_switch,
splits): Only match on TARGET_SH4.
From-SVN: r37907
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/config/sh/sh.md | 18 |
2 files changed, 13 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 93b0f9d..ebed5d0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2000-11-30 Alexandre Oliva <aoliva@redhat.com> + * config/sh/sh.md (fpu_switch0, fpu_switch1, movpsi, fpu_switch, + splits): Only match on TARGET_SH4. + * combine.c (try_combine): Disregard USEs when updating LOG_LINKS of subsequent insns. diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index de1f553..5973bb1 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -4295,7 +4295,7 @@ (define_expand "fpu_switch0" [(set (match_operand:SI 0 "" "") (match_dup 2)) (set (match_dup 1) (mem:PSI (match_dup 0)))] - "" + "TARGET_SH4" " { operands[1] = get_fpscr_rtx (); @@ -4309,7 +4309,7 @@ [(set (match_operand:SI 0 "" "") (match_dup 2)) (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4))) (set (match_dup 1) (mem:PSI (match_dup 3)))] - "" + "TARGET_SH4" " { operands[1] = get_fpscr_rtx (); @@ -4323,7 +4323,7 @@ (define_expand "movpsi" [(set (match_operand:PSI 0 "register_operand" "") (match_operand:PSI 1 "general_movsrc_operand" ""))] - "" + "TARGET_SH4" "") ;; The c / m alternative is a fake to guide reload to load directly into @@ -4336,9 +4336,11 @@ (define_insn "fpu_switch" [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r") (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))] - "! reload_completed - || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM - || GET_CODE (XEXP (operands[1], 0)) != PLUS" + "TARGET_SH4 + && (! reload_completed + || true_regnum (operands[0]) != FPSCR_REG + || GET_CODE (operands[1]) != MEM + || GET_CODE (XEXP (operands[1], 0)) != PLUS)" "@ ! precision stays the same lds.l %1,fpscr @@ -4354,7 +4356,7 @@ (define_split [(set (reg:PSI FPSCR_REG) (mem:PSI (match_operand:SI 0 "register_operand" "r")))] - "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" + "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" [(set (match_dup 0) (match_dup 0))] " { @@ -4368,7 +4370,7 @@ (define_split [(set (reg:PSI FPSCR_REG) (mem:PSI (match_operand:SI 0 "register_operand" "r")))] - "" + "TARGET_SH4" [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))] " { |