i386: Allow 64bit vector modes in general registers

Allow V8QI, V4HI and V2SI modes in 64bit general registers for
TARGET_64BIT and add alternatives using general registers
to 64bit vector logic instructions.

2021-05-19  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
	* config/i386/i386.h (VALID_INT_MODE_P):
	Add V8QI, V4HI and V2SI modes for TARGET_64BIT.
	* config/i386/i386.md (isa): Add x64_bmi.
	(enabled): Handle x64_bmi.
	* config/i386/mmx.md (mmx_andnot<MMXMODEI:mode>3):
	Add alternative using 64bit general registers.
	(*mmx_<any_logic:code><MMXMODEI:mode>3): Ditto.

3 files changed, 32 insertions, 22 deletions

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d15f9b2..53d503f 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1039,10 +1039,12 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    || (MODE) == SImode || (MODE) == DImode				\
    || (MODE) == CQImode || (MODE) == CHImode				\
    || (MODE) == CSImode || (MODE) == CDImode				\
+   || (MODE) == V4QImode || (MODE) == V2HImode				\
    || (TARGET_64BIT							\
        && ((MODE) == TImode || (MODE) == CTImode			\
-	   || (MODE) == TFmode || (MODE) == TCmode))			\
-   || (MODE) == V4QImode || (MODE) == V2HImode)
+	   || (MODE) == TFmode || (MODE) == TCmode			\
+	   || (MODE) == V8QImode || (MODE) == V4HImode			\
+	   || (MODE) == V2SImode)))
 
 /* Return true for modes passed in SSE registers.  */
 #define SSE_REG_MODE_P(MODE)						\
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 74e924f..2fc8fae 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -815,11 +815,12 @@
 (define_attr "movu" "0,1" (const_string "0"))
 
 ;; Used to control the "enabled" attribute on a per-instruction basis.
-(define_attr "isa" "base,x64,x64_sse2,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
+(define_attr "isa" "base,x64,nox64,x64_bmi,x64_sse2,x64_sse4,x64_sse4_noavx,
+		    x64_avx,x64_avx512bw,x64_avx512dq,
 		    sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
 		    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
 		    avx512bw,noavx512bw,avx512dq,noavx512dq,
-		    avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw,
+		    avx512vl,noavx512vl,
 		    avxvnni,avx512vnnivl"
   (const_string "base"))
 
@@ -829,6 +830,9 @@
 
 (define_attr "enabled" ""
   (cond [(eq_attr "isa" "x64") (symbol_ref "TARGET_64BIT")
+	 (eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT")
+	 (eq_attr "isa" "x64_bmi")
+	   (symbol_ref "TARGET_64BIT && TARGET_BMI")
 	 (eq_attr "isa" "x64_sse2")
 	   (symbol_ref "TARGET_64BIT && TARGET_SSE2")
 	 (eq_attr "isa" "x64_sse4")
@@ -837,14 +841,13 @@
 	   (symbol_ref "TARGET_64BIT && TARGET_SSE4_1 && !TARGET_AVX")
 	 (eq_attr "isa" "x64_avx")
 	   (symbol_ref "TARGET_64BIT && TARGET_AVX")
-	 (eq_attr "isa" "x64_avx512dq")
-	   (symbol_ref "TARGET_64BIT && TARGET_AVX512DQ")
 	 (eq_attr "isa" "x64_avx512bw")
 	   (symbol_ref "TARGET_64BIT && TARGET_AVX512BW")
-	 (eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT")
-	 (eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
+	 (eq_attr "isa" "x64_avx512dq")
+	   (symbol_ref "TARGET_64BIT && TARGET_AVX512DQ")
 	 (eq_attr "isa" "sse_noavx")
 	   (symbol_ref "TARGET_SSE && !TARGET_AVX")
+	 (eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
 	 (eq_attr "isa" "sse2_noavx")
 	   (symbol_ref "TARGET_SSE2 && !TARGET_AVX")
 	 (eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 7806b62..d847978 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1987,20 +1987,24 @@
   "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
 
 (define_insn "mmx_andnot<mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,r,x,x,v")
 	(and:MMXMODEI
-	  (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,x,v"))
-	  (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
+	  (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand"
+	    "0,r,0,x,v"))
+	  (match_operand:MMXMODEI 2 "register_mmxmem_operand"
+	    "ym,r,x,x,v")))]
   "TARGET_MMX || TARGET_MMX_WITH_SSE"
   "@
    pandn\t{%2, %0|%0, %2}
+   andn\t{%2, %1, %0|%0, %1, %2}
    pandn\t{%2, %0|%0, %2}
    vpandn\t{%2, %1, %0|%0, %1, %2}
    vpandnd\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
-   (set_attr "mmx_isa" "native,*,*,*")
-   (set_attr "type" "mmxadd,sselog,sselog,sselog")
-   (set_attr "mode" "DI,TI,TI,TI")])
+  [(set_attr "isa" "*,x64_bmi,sse2_noavx,avx,avx512vl")
+   (set_attr "mmx_isa" "native,*,*,*,*")
+   (set_attr "type" "mmxadd,bitmanip,sselog,sselog,sselog")
+   (set_attr "btver2_decode" "*,direct,*,*,*")
+   (set_attr "mode" "DI,DI,TI,TI,TI")])
 
 (define_insn "*andnot<mode>3"
   [(set (match_operand:VI_32 0 "register_operand" "=r,x,x,v")
@@ -2035,21 +2039,22 @@
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 
 (define_insn "*mmx_<code><mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,r,x,x,v")
         (any_logic:MMXMODEI
-	  (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x,v")
-	  (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
+	  (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,0,x,v")
+	  (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,r,x,x,v")))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
    && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "@
    p<logic>\t{%2, %0|%0, %2}
+   <logic>\t{%2, %0|%0, %2}
    p<logic>\t{%2, %0|%0, %2}
    vp<logic>\t{%2, %1, %0|%0, %1, %2}
    vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
-   (set_attr "mmx_isa" "native,*,*,*")
-   (set_attr "type" "mmxadd,sselog,sselog,sselog")
-   (set_attr "mode" "DI,TI,TI,TI")])
+  [(set_attr "isa" "*,x64,sse2_noavx,avx,avx512vl")
+   (set_attr "mmx_isa" "native,*,*,*,*")
+   (set_attr "type" "mmxadd,alu,sselog,sselog,sselog")
+   (set_attr "mode" "DI,DI,TI,TI,TI")])
 
 (define_expand "<code><mode>3"
   [(set (match_operand:VI_32 0 "register_operand")