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| author | Richard Sandiford <rsandifo@redhat.com> | 2004-08-23 08:25:56 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2004-08-23 08:25:56 +0000 |
| commit | e8bf0f3bacc5f3f4ae892f4df794cc23e41519b9 (patch) | |
| tree | e8feeb440b6f1a9015f356b7f8ece2d5b40d04f7 /gcc | |
| parent | 4d06ed0a96ce09cef95f80a7b2693410fb4a5da3 (diff) | |
| download | gcc-e8bf0f3bacc5f3f4ae892f4df794cc23e41519b9.zip gcc-e8bf0f3bacc5f3f4ae892f4df794cc23e41519b9.tar.gz gcc-e8bf0f3bacc5f3f4ae892f4df794cc23e41519b9.tar.bz2 | |
mips.md (mfhilo_[sd]i): Redefine using :GPR.
* config/mips/mips.md (mfhilo_[sd]i): Redefine using :GPR. Add mode
attribute.
From-SVN: r86420
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 22 |
2 files changed, 12 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ee5dde5..08c8713 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-08-23 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md (mfhilo_[sd]i): Redefine using :GPR. Add mode + attribute. + +2004-08-23 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md (length): Don't use mips_fetch_insns for indexed loads and stores. (*lwxc1_<mode>, *ldxc1_<mode>, *swxc1_<mode>, *sdxc1_<mode>): Name diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e42a607..2a8ca05 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4087,23 +4087,15 @@ beq\t%2,%.,1b\;\ ;; We cope with this by making the mflo and mfhi patterns use both HI and LO. ;; Operand 1 is the register we want, operand 2 is the other one. -(define_insn "mfhilo_di" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (unspec:DI [(match_operand:DI 1 "register_operand" "h,l") - (match_operand:DI 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "TARGET_64BIT" - "mf%1\t%0" - [(set_attr "type" "mfhilo")]) - -(define_insn "mfhilo_si" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (unspec:SI [(match_operand:SI 1 "register_operand" "h,l") - (match_operand:SI 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] +(define_insn "mfhilo_<mode>" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") + (match_operand:GPR 2 "register_operand" "l,h")] + UNSPEC_MFHILO))] "" "mf%1\t%0" - [(set_attr "type" "mfhilo")]) + [(set_attr "type" "mfhilo") + (set_attr "mode" "<MODE>")]) ;; Patterns for loading or storing part of a paired floating point ;; register. We need them because odd-numbered floating-point registers |