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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2021-05-17 11:57:30 +0000 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@linaro.org> | 2021-05-17 11:57:30 +0000 |
| commit | e87d568e9e3e331e22850127308abedd0642e5e8 (patch) | |
| tree | e4ccde636c98bec16e1b4a4b7de5096e474d6104 /gcc | |
| parent | 325187841aa66f0d03403d41fe9e696d094588b9 (diff) | |
| download | gcc-e87d568e9e3e331e22850127308abedd0642e5e8.zip gcc-e87d568e9e3e331e22850127308abedd0642e5e8.tar.gz gcc-e87d568e9e3e331e22850127308abedd0642e5e8.tar.bz2 | |
testsuite/arm: Improve mve-vshr.c
Vector right shifts by immediate use vshr, while right shifts by
vectors instead use vneg and vshl.
This patch adds the corresponding scan-assembler-times that were
missing.
2021-05-17 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* gcc.target/arm/simd/mve-vshr.c: Add more scan-assembler-times.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c index d4e658c..d4258e9 100644 --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c @@ -55,5 +55,12 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm) /* MVE has only 128-bit vectors, so we can vectorize only half of the functions above. */ +/* Vector right shifts use vneg and left shifts. */ +/* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */ + + +/* Shift by immediate. */ /* { dg-final { scan-assembler-times {vshr.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {vshr.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ |