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author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2020-12-18 10:00:34 +0100 |
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committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-09 10:31:48 +0100 |
commit | e7c8f5005bf87e4bd95b25fb31430eef7e58097e (patch) | |
tree | ca69810256667d14f6c2ab2e55975667730a42b7 /gcc | |
parent | d699d32f47833cfab959a810dad48774c021c677 (diff) | |
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RISC-V: costs: handle BSWAP
The BSWAP operation is not handled in rtx_costs. Add it.
With Zbb, BSWAP for XLEN is a single instruction; for smaller modes,
it will expand into two.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Add BSWAP.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/riscv.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 32f9ef9..ab6c745 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2562,6 +2562,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND); return false; + case BSWAP: + if (TARGET_ZBB) + { + /* RISC-V only defines rev8 for XLEN, so we will need an extra + shift-right instruction for smaller modes. */ + *total = COSTS_N_INSNS (mode == word_mode ? 1 : 2); + return true; + } + return false; + case FLOAT: case UNSIGNED_FLOAT: case FIX: |