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authorKewen Lin <linkw@linux.ibm.com>2021-07-08 22:00:18 -0500
committerKewen Lin <linkw@linux.ibm.com>2021-07-08 22:00:18 -0500
commitdf85baa5687170cbca8450a59cf17f3157b1d61d (patch)
treee0276473e55b3742ec19db524275bb90c97bd683 /gcc
parentc3d1aa891cbc4d78408481d528d8f0927c2a0379 (diff)
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test/rs6000: Add case to cover vector division
This patch is to add one test case to check if vectorizer can exploit vector division instrutions newly introduced by Power10. gcc/testsuite/ChangeLog: * gcc.target/powerpc/div-vectorize-1.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c46
1 files changed, 46 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c
new file mode 100644
index 0000000..6208b2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c
@@ -0,0 +1,46 @@
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */
+
+/* Test vectorizer can exploit ISA 3.1 instructions Vector Divide
+ Signed/Unsigned Word/Doubleword for word/doubleword division. */
+
+#define N 128
+
+extern signed int si_a[N], si_b[N], si_c[N];
+extern unsigned int ui_a[N], ui_b[N], ui_c[N];
+extern signed long long sd_a[N], sd_b[N], sd_c[N];
+extern unsigned long long ud_a[N], ud_b[N], ud_c[N];
+
+__attribute__ ((noipa)) void
+test_si ()
+{
+ for (int i = 0; i < N; i++)
+ si_c[i] = si_a[i] / si_b[i];
+}
+
+__attribute__ ((noipa)) void
+test_ui ()
+{
+ for (int i = 0; i < N; i++)
+ ui_c[i] = ui_a[i] / ui_b[i];
+}
+
+__attribute__ ((noipa)) void
+test_sd ()
+{
+ for (int i = 0; i < N; i++)
+ sd_c[i] = sd_a[i] / sd_b[i];
+}
+
+__attribute__ ((noipa)) void
+test_ud ()
+{
+ for (int i = 0; i < N; i++)
+ ud_c[i] = ud_a[i] / ud_b[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
+/* { dg-final { scan-assembler-times {\mvdivsw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvdivuw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvdivud\M} 1 } } */