(const_umulsi3_highpart): Disable for TARGET_M68060.

(ftruncdf2, ftruncsf2, muldf3, mulsidi3): Likewise.
(smulsi3_highpart, umulsi3_highpart, umulsidi3): Likewise.

From-SVN: r11296

1 files changed, 25 insertions, 15 deletions

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index d18666b..bfe5e58 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -92,6 +92,16 @@
 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
 ;;- than "".
 
+;;- Information about 68060 port.
+
+;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
+;;- be emulated in software by the OS.  It is faster to avoid these 
+;;- instructions and issue a library call rather than trapping into 
+;;- the kernel.  The affected instructions are: divs.l <ea>,Dr:Dq;
+;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq, fintrz;
+;;- and fscale.  The TARGET_68060 flag turns the use of the opcodes 
+;;- off.
+
 
 ;;- 		FPA port explanation:
 
@@ -1919,7 +1929,7 @@
 (define_insn "ftruncdf2"
   [(set (match_operand:DF 0 "general_operand" "=f")
 	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
-  "TARGET_68881 && !TARGET_68040"
+  "TARGET_68881 && !TARGET_68040 && !TARGET_68060"
   "*
 {
   if (FP_REG_P (operands[1]))
@@ -1930,7 +1940,7 @@
 (define_insn "ftruncsf2"
   [(set (match_operand:SF 0 "general_operand" "=f")
 	(fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
-  "TARGET_68881 && !TARGET_68040"
+  "TARGET_68881 && !TARGET_68040 && !TARGET_68060"
   "*
 {
   if (FP_REG_P (operands[1]))
@@ -2975,7 +2985,7 @@
 	  (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
 					     (zero_extend:DI (match_dup 2)))
 				    (const_int 32))))])]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "")
 
 (define_insn ""
@@ -2986,7 +2996,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
 					   (zero_extend:DI (match_dup 2)))
 				  (const_int 32))))]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "mulu%.l %2,%3:%0")
 
 ; Match immediate case.  For 2.4 only match things < 2^31.
@@ -3001,7 +3011,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
 					   (match_dup 2))
 				  (const_int 32))))]
-  "TARGET_68020
+  "TARGET_68020 && !TARGET_68060
    && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
   "mulu%.l %2,%3:%0")
 
@@ -3014,7 +3024,7 @@
 	  (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
 					     (sign_extend:DI (match_dup 2)))
 				    (const_int 32))))])]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "")
 
 (define_insn ""
@@ -3025,7 +3035,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
 					   (sign_extend:DI (match_dup 2)))
 				  (const_int 32))))]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "muls%.l %2,%3:%0")
 
 (define_insn ""
@@ -3036,7 +3046,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
 					   (match_dup 2))
 				  (const_int 32))))]
-  "TARGET_68020
+  "TARGET_68020 && !TARGET_68060
    /* This test is a noop on 32 bit machines,
       but important for a cross-compiler hosted on 64-bit machines.  */
    && INTVAL (operands[2]) <= 0x7fffffff
@@ -3052,7 +3062,7 @@
 		     (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
 	    (const_int 32))))
      (clobber (match_dup 3))])]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "
 {
   operands[3] = gen_reg_rtx (SImode);
@@ -3076,7 +3086,7 @@
 		   (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "mulu%.l %3,%0:%1")
 
 (define_insn "const_umulsi3_highpart"
@@ -3087,7 +3097,7 @@
 		   (match_operand 3 "const_uint32_operand" ""))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "mulu%.l %3,%0:%1")
 
 (define_expand "smulsi3_highpart"
@@ -3099,7 +3109,7 @@
 		     (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
 	    (const_int 32))))
      (clobber (match_dup 3))])]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "
 {
   operands[3] = gen_reg_rtx (SImode);
@@ -3123,7 +3133,7 @@
 		   (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "muls%.l %3,%0:%1")
 
 (define_insn "const_smulsi3_highpart"
@@ -3134,7 +3144,7 @@
 		   (match_operand 3 "const_sint32_operand" ""))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020"
+  "TARGET_68020 && !TARGET_68060"
   "muls%.l %3,%0:%1")
 
 (define_expand "muldf3"
@@ -3191,7 +3201,7 @@
   "*
 {
   if (GET_CODE (operands[2]) == CONST_DOUBLE
-      && floating_exact_log2 (operands[2]) && !TARGET_68040)
+      && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
     {
       int i = floating_exact_log2 (operands[2]);
       operands[2] = gen_rtx (CONST_INT, VOIDmode, i);